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Anonymous
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Problem with Reference design ZedBoard

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I have tried chapter 2 tutorial using Vivado SDK and ZedBoard with wondows 7 machine from the Reference Design Tutorial which is available in attachment, and can also be found from the lik below.  

 

"Zynq Concepts, Tools, and Techniques on ZedBoard"

 

http://zedboard.org/support/design/1521/11

 

The chapter 2 tutorial works well but there is a problem with tutorial in chapter 3. I have followed all the steps of this tutorial until Figure 3-7 on page 42. The blue DONE LED light turns  up according to point number 10 but nothing appears on the Tera Term termina, l even I could not type anything on the tera terminal.  

 

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Contributor
Contributor
22,773 Views
Registered: ‎12-09-2015

Re: Problem with Reference design ZedBoard

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9 Replies
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Scholar
Scholar
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Registered: ‎02-27-2008

Re: Problem with Reference design ZedBoard

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Are you using 2014.2?

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
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Anonymous
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11,990 Views

Re: Problem with Reference design ZedBoard

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I am using Vivado 2015.4

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Anonymous
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11,983 Views

Re: Problem with Reference design ZedBoard

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Before reference design I also have tried all demos on ZedBoard mentioned in Getting Started Guide "GS-AES-Z7EV-7Z020-G-V7" available in attachment. All demos works well even including these which require Term Tera. 

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Contributor
Contributor
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Registered: ‎12-09-2015

Re: Problem with Reference design ZedBoard

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Are you going for run configuration or debug??
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Anonymous
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11,908 Views

Re: Problem with Reference design ZedBoard

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I am running Chapter 3 "Embedded system design using the Zynq Processing System and Programmable Logic" which is configuration mode I guess not debug mode. 

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Contributor
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Registered: ‎12-09-2015

Re: Problem with Reference design ZedBoard

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Have you connected the teraterm correctly? Choose right port?? Set the baud rate correctly?? If you have you are probably missing something in the design.
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Anonymous
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11,797 Views

Re: Problem with Reference design ZedBoard

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All settings are ok. Now it works. The problem was with preset Zynq PS IP before validating design. It was not done properly.  

 

I have another question regarding interfacing with DDR 3 memory on ZedBoard. Is is necessary to involve PS to communicate with DDR memory ? Is there any IP available to send or receive the data from Zynq to DDR ? 

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Contributor
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Registered: ‎12-09-2015

Re: Problem with Reference design ZedBoard

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I am sorry @Anonymous. I didnt understand your question.
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Contributor
Contributor
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Registered: ‎12-09-2015

Re: Problem with Reference design ZedBoard

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