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Visitor mbussen
Visitor
365 Views
Registered: ‎05-29-2019

Problems with LVDS clock input to XC7A35T

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We are attempting to use an ILSI ISM64 to provide an LVDS clock on the MRCC pins T14 and T15 of a XC7A35T-L2CSG325E FPGA.  The VCCO for the bank in question is 3.3V.  Below is a snippet of our schematic showing the relevant connections:

schematic.png

 

 

 

 

 

 

 

 

The 165MHz clock does appear to be received correctly by the FPGA and can be output onto a test pin to confirm, but the general signal quality looks very poor and we are seeing some odd behavior.  The scope capture below shows the differential voltage seen at a point very close to the FPGA pins.  The trace in blue is with the AC coupling caps C270/C271 in place, and looks more or less correct, although the rise and fall times are not ideal and the waveforms look a bit rounded.  The trace in white is with NO Ac coupling in place (caps replaced with 0 ohm resistors) and is swinging well outside of the specified voltage range for an LVDS signal.

no ac coupling comparison.png

I have disconnected this ISM64 oscillator from the FPGA and just measured the differential LVDS output through a 100 ohm differential termination resistor, which looks correct:

ILSI diff.png

Any ideas as to why removing the AC coupling caps is causing this issue given that the common mode output voltage and differential swing of the ISM64 seems to match up perfectly with the LVDS_25 DC specifications of the Artix FPGA?

Here is the code for the input buffer in the verilog file:

IBUFGDS ibufgds_clk_165mhz
(
	.I		( refclk_165mhz_p	),
	.IB		( refclk_165mhz_n	),
	.O		( refclk_165mhz_se	)
);

And the declarations in the XDC file:

set_property PACKAGE_PIN T14 [get_ports refclk_165mhz_p]
set_property PACKAGE_PIN T15 [get_ports refclk_165mhz_n]

set_property IOSTANDARD LVDS_25 [get_ports refclk_165mhz_p]
set_property IOSTANDARD LVDS_25 [get_ports refclk_165mhz_n]

 

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Scholar drjohnsmith
Scholar
347 Views
Registered: ‎07-09-2009

Re: Problems with LVDS clock input to XC7A35T

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the input of the fpag has a dc bias circuit,
but please check the data sheet, as some of the fpgas need an external bias to use ac coupling,

if you take off the ac coupling capacitors, your driving a DC voltage with resistance by another dc source, think thevlin equivalent circuits.

Oh, and an LVDS driver is a current source, so the driver is going to try to crank up its voltage to get the current out / in,

keep the capacitors,

the slower rise you see compared to a pure resistance,
is not unusual for a capacitive input to the fpga,
but it very much dependent upon your layout,

whats the rise time your seeing ? ( sorry cant see to much on the phone screen )
<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
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2 Replies
Scholar drjohnsmith
Scholar
348 Views
Registered: ‎07-09-2009

Re: Problems with LVDS clock input to XC7A35T

Jump to solution
the input of the fpag has a dc bias circuit,
but please check the data sheet, as some of the fpgas need an external bias to use ac coupling,

if you take off the ac coupling capacitors, your driving a DC voltage with resistance by another dc source, think thevlin equivalent circuits.

Oh, and an LVDS driver is a current source, so the driver is going to try to crank up its voltage to get the current out / in,

keep the capacitors,

the slower rise you see compared to a pure resistance,
is not unusual for a capacitive input to the fpga,
but it very much dependent upon your layout,

whats the rise time your seeing ? ( sorry cant see to much on the phone screen )
<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
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Visitor mbussen
Visitor
301 Views
Registered: ‎05-29-2019

Re: Problems with LVDS clock input to XC7A35T

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The rise and fall times are around 700-800 ps, which I suspect is acceptable (the FPGA is able to resolve the 165 MHz clock and output it on a test pin) but seems like it could be improved.

I believe you are correct that these single-ended inputs need a DC bias after the AC coupling caps per Figure 1-72 in the SelectIO User Guide because the Artix LVDS_25 inputs require an input common-mode voltage of 1.2V (typical).  After I added the DC bias the differential capture looked a little bit better:

 

ism64 dc bias diff.png

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