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Explorer
Explorer
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Registered: ‎09-14-2018

Pulse Width Negative Slack on OSERDESE3 (Kintex Ultrascale, Vivado 2018.3).

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Hello,

I am modifying the existing Kintex-7 design for Ultrascale family. I have a failure due to the Pulse Width negative slack. The clock is used for OSERDESE3 (OSERDESE2 for Kintex-7). I am not sure if there are different timing requirements? The clock generation is similar, and the clock frequency is not high (133 MHz and 266 MHz for DDR, Width 4). When I tried to slightly reduce the clock frequency (changed to 125 MHz and 250 MHz respectively) the slack still stayed the same (max -0.150ns)

What might be wrong?

Can the error message be ignored?       

Thank you.

 

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Registered: ‎01-22-2015

@arotenst 

When Vivado reports "Pulse Width" problems, this means that your design is trying to operate outside the specifications for some component - and usually it is a clocking problem (ie. your clock frequency is either too high or too low).

You will note that UltraScale devices have circuits/primitives that are classified as either "Component Mode" or "Native Mode" (ref. UG571).  Essentially, Native Mode primitives are the fundamental building blocks in UltraScale.  Xilinx has bundled the Native mode primtives to create Component Mode primitives such as the OSERDESE3 that you are using.  Having the OSERDESE3 makes it easier for you and me to transition from the old 7-Series OSERDESE2.  However, you could use the High Speed SelectIO Wizard (ref PG188) to create your own OSERDES-like structure with Native Mode primitives.  This Native Mode OSERDES can operate at higher frequencies than the OSERDESE3.  Oddly, the Native Mode OSERDES has a low frequency limit of about 150MHz (eg. see Tables 23 and 24 is DS892(v1.18)).  The OSERDESE3 can operate at frequencies much lower than 150MHz.

Anyway, double-check that you are clocking the OSERDESE3 as shown in Fig 16 or in Fig 22 of XAPP1324(v1.1).  Also, note from Table 2-8 of UG571(v1.12) that OSERDESE3 has a limited number of operating modes (DDR with 8:1 or 4:1) and (SDR with 4:1 or 2:1).  Finally, as a test, try increasing your clock frequency above 150MHz (SDR) to see if Pulse Width problems disappear.

Then, if you still have problems, show us exactly how you instantiated the OSERDESE3, exactly how you are clocking it, and show us the Pulse Width report (pg 48 of UG906(v2020.1)) for your project.

Cheers,
Mark

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300 Views
Registered: ‎01-22-2015

@arotenst 

When Vivado reports "Pulse Width" problems, this means that your design is trying to operate outside the specifications for some component - and usually it is a clocking problem (ie. your clock frequency is either too high or too low).

You will note that UltraScale devices have circuits/primitives that are classified as either "Component Mode" or "Native Mode" (ref. UG571).  Essentially, Native Mode primitives are the fundamental building blocks in UltraScale.  Xilinx has bundled the Native mode primtives to create Component Mode primitives such as the OSERDESE3 that you are using.  Having the OSERDESE3 makes it easier for you and me to transition from the old 7-Series OSERDESE2.  However, you could use the High Speed SelectIO Wizard (ref PG188) to create your own OSERDES-like structure with Native Mode primitives.  This Native Mode OSERDES can operate at higher frequencies than the OSERDESE3.  Oddly, the Native Mode OSERDES has a low frequency limit of about 150MHz (eg. see Tables 23 and 24 is DS892(v1.18)).  The OSERDESE3 can operate at frequencies much lower than 150MHz.

Anyway, double-check that you are clocking the OSERDESE3 as shown in Fig 16 or in Fig 22 of XAPP1324(v1.1).  Also, note from Table 2-8 of UG571(v1.12) that OSERDESE3 has a limited number of operating modes (DDR with 8:1 or 4:1) and (SDR with 4:1 or 2:1).  Finally, as a test, try increasing your clock frequency above 150MHz (SDR) to see if Pulse Width problems disappear.

Then, if you still have problems, show us exactly how you instantiated the OSERDESE3, exactly how you are clocking it, and show us the Pulse Width report (pg 48 of UG906(v2020.1)) for your project.

Cheers,
Mark

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Explorer
Explorer
217 Views
Registered: ‎09-14-2018

Hi Mark,

Thank you for the very detailed explanations. It turned out that the problem was with using two MMCM outputs instead of the single one (XAPP1324, Figure 16). Unfortunately, the Vivado error was confusing.

Thanks again,

Alex

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