This query is regarding one of our application scenarios.
I am using a Spartan-6 LX16 FPGA and have a 161 MHz gapped clock coming on one of the input GCLK pins.
If you have a gapped clocked then using the Clocking Wizard (DCM or PLL) is not a good idea.
The input clock to the Clocking Wizard needs to be continuous.
When the CLKIN stops then the Clocking Wizard need to be Reset and then you've to wait for it to reLOCK which can take 100us and that probably will have a negative impact on your design.