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Registered: ‎05-16-2019

Query regarding gapped clock clean-up using Clocking Wizard in Spartan 6

This query is regarding one of our application scenarios.

I am using a Spartan-6 LX16 FPGA and have a 161 MHz gapped clock coming on one of the input GCLK pins.

  • Can we use the Clocking Wizard v3.1 Core IP to source a cleaned 161 MHz clock from the mentioned input?
  • Do we have an option to change the loop bandwidth in this PLL instantiation?
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Community Manager
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Registered: ‎08-08-2007

Hi @utsuk_sharma 

 

If you have a gapped clocked then using the Clocking Wizard (DCM or PLL)  is not a good idea.

The input clock  to the Clocking Wizard needs to be continuous. 

When the CLKIN stops then the Clocking Wizard need to be Reset and then you've to wait for it to reLOCK which can take 100us and that probably will have a negative impact on your design. 

 

 

Thanks,
Sandy

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