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Explorer
Explorer
430 Views
Registered: ‎10-07-2016

Question about BUFR "Divide by 1" Mode in Kintex7

Dear colleagues,

I have a question about the BUFR primitive in a Kintex7 device.
When I use the BUFR in "divide by 1" mode, can it happen that the phase between input and output clock can be either 0° or 180°, in dependcy when CE is released related to the input clock?

Best regards

stgateizo

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8 Replies
Voyager
Voyager
420 Views
Registered: ‎05-11-2015

 

I don't think so. Fig 2-22 in UG472 may hold some clues. Keep in mind that divide by 1 and bypass are different in terms of delay (thus phase)

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Explorer
Explorer
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Registered: ‎10-07-2016

Hi joancab,

well I have made some tests now, and it seems that there can happen a phase shift of 0° or 180°, in dependecny if  CE is going high with a rising, or falling input clock edge. I set now the BUFR into "Bypass" mode, and now the pahse shift is stable (zero phase shift).

Regards

stgateizo

Voyager
Voyager
402 Views
Registered: ‎05-11-2015

 

That's quite interesting. I would prefer to think you violate some timing requirements in one of these experiments. How do you measure phase? What frequency?

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Explorer
Explorer
356 Views
Registered: ‎10-07-2016

Hi joancab,

I cannot measure the phase directly, but let me explain why I think that the behavior is as I have described as before:

  1. I use the BUFR in the input clock path, in order to clock in data with an IDDR primitive. When I set the BUFR attribute BUFR_DIVIDE <= "1", then the divide by 1 mode is active. In this case, after power-on I can sometimes see that data are provided in the wrong order (IDDR output Q1 and Q2 are mixed up) with a probabiltiy of 50%. When I set the BUFR attribute BUFR_DIVIDE <= "BYPASS", then the data are always in the correct order at Q1 an

  2. When you look to figure 2-22 below (or ug472 page 53), you can see that the input clock edge, which follows after CE goes high will lead to a rising clock edge on the output. So if the input clock edge is a rising clock edge the phase will be 0°. If the input clock edge was a falling clock edge, the pahse can be 180°.
    Of course it is not exactly 0° or 180°, since the BUFR itself has probably also some latency.

Pic1.PNG

Well if you don't belive it, please make a little example design, where you route the clock before the BUFR and after the BUFR to any output pins, and measure the phase shift, after each power-cycle. You have to load the FPGA from FLASH for this scenario... You will not see this issue when you use JTAG for loading the FPGA...
Well i have not the time for doing such basic tests. I already spent too much effort for debugging this issue, and you know time is money.

Best regards

stgateizo

Voyager
Voyager
351 Views
Registered: ‎05-11-2015

 

I agree with your way of measuring phase. So you mean CE is captured at both input clock edges and output comes after so it can have that 0/180 phase. It looks like something Xilinx could be interested in, at least, document to warn people in the future.

 

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Explorer
Explorer
346 Views
Registered: ‎10-07-2016

Hi joancab,

well the default value is "BYPASS". I think most developers even do not know that you can use it as divider. But when you use it as divider, you are faced to this beahvior...

Kind regards

stgateizo

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Registered: ‎01-22-2015

When you toggle CE on the BUFR, it will behave differently for BUFR_DIVIDE=BYPASS and BUFR_DIVIDE=1. 

For example, when you toggle CE, the output of the BUFR with BUFR_DIVIDE=BYPASS may start with a falling clock edge whereas the output of the BUFR with BUFR_DIVIDE=1 may start a little later with a rising clock edge. 

However, the BUFR input and output clock will always end up very nearly phase-aligned whether you use BUFR_DIVIDE=BYPASS or BUFR_DIVIDE=1. 

It is best to control the startup of BUFR-produced clocks using the BUFR Alignment method described in Appendix A of UG472.  This Alignment is especially important if you are using BUFR_DIVIDE values greater than 1, otherwise the phase relationship between clock outputs from separate BUFR could change every time you power-up the FPGA.

In short, the BUFR Alignment method is:

  • all BUFR are fed from a common buffer with CE (typically BUFMRCE)
  • set CE=1 on all BUFR
  • stop the clock input to all BUFR using CE=0 on BUFMRCE
  • toggle the CLR pin on all BUFR
  • start the clock input to all BUFR using CE=1 on BUFMRCE

Cheers,
Mark

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Explorer
Explorer
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Registered: ‎10-07-2016

Hi Mark,

your statement "However, the BUFR input and output clock will always end up very nearly phase-aligned whether you use BUFR_DIVIDE=BYPASS or BUFR_DIVIDE=1. ", does not match to my experiences.

Well I only chagned the BUFR from "Divide by 1" to "Bypass", and I was able to sample the data properly.
As long as nobody is preparing an example design, which allows you to check the phase realtionship with an external oscilloscope, I do not belive it.

Kind regards

stgateizo

 

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