11-30-2020 06:46 AM
I have a question about the BUFR primitive in a Kintex7 device.
When I use the BUFR in "divide by 1" mode, can it happen that the phase between input and output clock can be either 0° or 180°, in dependcy when CE is released related to the input clock?
11-30-2020 07:55 AM
well I have made some tests now, and it seems that there can happen a phase shift of 0° or 180°, in dependecny if CE is going high with a rising, or falling input clock edge. I set now the BUFR into "Bypass" mode, and now the pahse shift is stable (zero phase shift).
11-30-2020 08:00 AM - edited 11-30-2020 08:02 AM
That's quite interesting. I would prefer to think you violate some timing requirements in one of these experiments. How do you measure phase? What frequency?
12-01-2020 01:09 AM - edited 12-01-2020 01:11 AM
I cannot measure the phase directly, but let me explain why I think that the behavior is as I have described as before:
Well if you don't belive it, please make a little example design, where you route the clock before the BUFR and after the BUFR to any output pins, and measure the phase shift, after each power-cycle. You have to load the FPGA from FLASH for this scenario... You will not see this issue when you use JTAG for loading the FPGA...
Well i have not the time for doing such basic tests. I already spent too much effort for debugging this issue, and you know time is money.
12-01-2020 01:24 AM
I agree with your way of measuring phase. So you mean CE is captured at both input clock edges and output comes after so it can have that 0/180 phase. It looks like something Xilinx could be interested in, at least, document to warn people in the future.
12-01-2020 01:44 AM
well the default value is "BYPASS". I think most developers even do not know that you can use it as divider. But when you use it as divider, you are faced to this beahvior...
12-03-2020 05:49 PM
When you toggle CE on the BUFR, it will behave differently for BUFR_DIVIDE=BYPASS and BUFR_DIVIDE=1.
For example, when you toggle CE, the output of the BUFR with BUFR_DIVIDE=BYPASS may start with a falling clock edge whereas the output of the BUFR with BUFR_DIVIDE=1 may start a little later with a rising clock edge.
However, the BUFR input and output clock will always end up very nearly phase-aligned whether you use BUFR_DIVIDE=BYPASS or BUFR_DIVIDE=1.
It is best to control the startup of BUFR-produced clocks using the BUFR Alignment method described in Appendix A of UG472. This Alignment is especially important if you are using BUFR_DIVIDE values greater than 1, otherwise the phase relationship between clock outputs from separate BUFR could change every time you power-up the FPGA.
In short, the BUFR Alignment method is:
12-04-2020 04:55 AM
your statement "However, the BUFR input and output clock will always end up very nearly phase-aligned whether you use BUFR_DIVIDE=BYPASS or BUFR_DIVIDE=1. ", does not match to my experiences.
Well I only chagned the BUFR from "Divide by 1" to "Bypass", and I was able to sample the data properly.
As long as nobody is preparing an example design, which allows you to check the phase realtionship with an external oscilloscope, I do not belive it.