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Visitor
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Registered: ‎01-01-2018

Question about Vivado FlipFlop generation

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Hi, I was reading a document "Vivado Design Suite User Guide: Synthesis" to know which syntax of the Verilog infers

the correct and efficient FF that maximally utilize the Xilinx hardware platform. 

 

During a reading, I've encountered below sentence and cannot figure out what it means.

 

Avoid operational set/reset logic whenever possible. There may be other, less
expensive, ways to achieve the desired effect, such as taking advantage of the circuit
global reset by defining an initial content.

 

As far as I know, FF should contain the reset or set signal to initialize the data, but it says do not use reset/ set signal.

Does it mean by putting initialization process in the initial begin end block?

 

What does it mean by "circuit global reset by defining an initial content?"

 

One more question about Flip-Flop initialization. The document said that 

"To initialize the content of a Register at circuit power-up, specify a default value for the
signal during declaration."

 

As far as I know, we can only initialize a content of register when we test a circuit in simulation mode. 

I cannot understand how can we initialize the circuit to make it have a default value when it boots up. 

I appreciate any helps. 

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Scholar
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Registered: ‎03-22-2016

@jaehyuk  It is controversial

Get Smart About Reset: Think Local, Not Global

https://www.xilinx.com/support/documentation/white_papers/wp272.pdf

 

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Registered: ‎03-22-2016

@jaehyuk  It is controversial

Get Smart About Reset: Think Local, Not Global

https://www.xilinx.com/support/documentation/white_papers/wp272.pdf

 

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Visitor
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Registered: ‎01-01-2018
Wow thanks for a good reference. By the way, I've added one more question related to Flipflop, its initialization. Could you give me an answer? Thanks a lot
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Registered: ‎03-22-2016

@jaehyuk Yes, on FPGAs it is completely valid to initialize internal state on initial blocks. Not so in ASICs though.

 

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Registered: ‎04-26-2015

jaehyuk wrote:

As far as I know, we can only initialize a content of register when we test a circuit in simulation mode. 



This seems to be a common fallacy. I was taught much the same at university - "you can't provide initial values in hardware". Actually, pretty much any FPGA you can buy (certainly back to the Spartan 2 series, possibly all the way back to the original XC2000) can support initial values. Same for devices from Altera/Lattice/Microsemi.

 

The initial values are included in the bitstream, and if you don't include them then ISE/Vivado will set them to zero. If you trigger an FPGA reset, it'll reload the bitstream and set new initial values for all of those bits.

 

As far as I know, the only exceptions in Xilinx FPGAs are some of the special-purpose logic blocks. I don't think you can define initial values for the DSP or Block RAM internal registers (although you can define a block RAM initial contents), nor can you define the initial contents of an UltraRAM.

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Registered: ‎03-22-2016

@u4223374 @jaehyuk  I have looked up another day - even HLS uses initial blocks.

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