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Participant
Participant
2,281 Views
Registered: ‎09-26-2016

Question on runtime changing the CLKOUT out of the MMCM

Hi,

 

Into Artix 7, I would like to implement MMCM with the ability to change CLKOUT during the operation on the command (via UART communication). The generated clock signal would be used as a clock of the SPI interface (Artix would be master).

 

I read the "7 Series Clocking Resources" user guide and "MMCM and PLL Dynamic Reconfiguration" application note and things are pretty clear to me. But I would like to ask a few questions anyway:

 

1. Let say I want to achieve SPI clocks from as low as possible to the max of 30 MHz. To get lowest possible clock I would configure CLKOUT4 and CLKOUT6 in cascade mode, so the VCO could be divided by 128*128 = 16384. If VCO is lowest possible (600 MHz), than, I am able to achieve 36.6 kHz clock. This is done through the "High Time" and "Low Time" parameters in DRP registers, am I right?

 

2. If VCO runs at 600 MHz, then the steps at around 30 MHz CLKOUT are a little big. Let say, 600 MHz / (4*6) = 25 MHz and 600 MHz / (6*6) = 16.6 MHz. In first example, low and high time for CLKOUT4 are 2, for CLKOUT6 are 3 VCO clocks. In second example,  low and high time for CLKOUT4 and CLKOUT6 are both 3 VCO clocks. If my math is correct, then this steps are too large. This would be improved if I would be able to increase also VCO frequency on the runtime. Is that possible? If yes, which parameter in DRP registers must be changed?

 

3. I would like to drive that clock to the output pin. Are there any output pins which are faster? Capable of faster switching?

 

4. I saw in the reference design of the MMCM that CLKFBOUT is not directly connected to the CLKFBIN with a simple wire, but it is driven through an additional BUFG primitive. Is that necessary and what is the actual reason of doing that?

 

I would be very grateful to help me clarify those things.

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Guide
Guide
2,266 Views
Registered: ‎01-23-2009

In general, for things like this it is best not to muck with the clock...

 

Making things "slower" is never a problem - just add wait states.

 

So, run your design at (say) 100MHz. If you want the SPI to work at 30MHz, then just operate the SPI state machine on every 3rd clock. If you want to run it at 30kHz, then just operate on every 3000th clock... Do this completely synchronously - have a counter that counts from N to 0 (where N is anywhere from 2999 to 2), and on the 0 count (which is where you reload), generate an enable. Then, in all your state machine code just do

 

always @(posedge clk)

begin

  if (enable)

  begin

    <do everything>

  end

end

 

This is far simpler and less error prone than mucking with the DRP of the MMCM...

 

Avrum

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Scholar
Scholar
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Registered: ‎03-22-2016

@avrumw Dividing the clock rate by 3 is a good interview question btw...

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Participant
Participant
2,187 Views
Registered: ‎09-26-2016

Thank you for your reply.

 

I have a current design created like this. And it works, as you said. But the problem is, when the higher frequencies are required (> 10 MHz), clock divider is small and the gaps between two consecutive are too large.

 

For example:

- every 3rd clock: 100 MHz / 3 = 33.3 MHz

- every 4th clock: 100 MHz / 4 = 25 MHz

- every 5th clock: 100 MHz / 5 = 20 MHz

 

The purpose of this SPI master interface is testing the slave device. We want to have a full control on frequency, data length, maybe even on duty cycle to see how slave device reacts and where exactly are its limits.

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Participant
Participant
2,186 Views
Registered: ‎09-26-2016

@hbucher what exactly did you mean with dividing by 3? In my first post I wrote that I would set "High Time" to 3 and "Low Time" to 3 as well. Is not that effectively dividing by 6?

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Scholar
Scholar
2,139 Views
Registered: ‎03-22-2016

@matic

http://www.referencedesigner.com/tutorials/verilogexamples/verilog_ex_06.php

 

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