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Explorer
Explorer
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Registered: ‎07-10-2008

Question regarding to Xapp1017 for converting LVDS serial data to parallel data

We have used the example in Xapp1017 as reference to convert LVDS serial data to parallel data .

Currently, we have a question regarding to bitslip module; in UG471_7Series_SelectIO, it is mentioned updated parallel data is triggered by clock CLKDIV and bitslip.

1'.png

In our hardware design output as attached in above figure, PIX_clk is the CLKDIV, SYNC_OUT is the output parallel data, but when bitslip is HIGH and PIX_clk is toggled HIGH, SYNC_OUT is not updated until few clocks after as marked in timing 2. Please let us know, how can we shift SYNC_OUT data to the correct position?

无标题.png

In the simulation result picture, SYNC_OUT is updated one clock after bitslip is HIGH and PIX_clk is toggled as marked timing 1 and 2.

Many thanks for any your suggestions.

David.

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Explorer
Explorer
141 Views
Registered: ‎07-10-2008

Re: Question regarding to Xapp1017 for converting LVDS serial data to parallel data

any suggestions?
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