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Visitor tyler.wilson
Visitor
7,876 Views
Registered: ‎05-08-2015

Reading a differential signal into the Kintex 7 KC705

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I am attempting to read a differential signal into the FPGA: i_SCLK_P and i_SCLK_N. I want to trigger my ILA on a rising edge of i_SCLK. I am unable to contrain my pins correctly. I am getting the following error:

 

  • [Place 30-64] Illegal IOStandard configured for port 'i_SCLK_N'. I/O port 'i_SCLK_N' is differential, but has single-ended IOStandard value LVCMOS25.

I have then attempted to change my IOStandard to LVDS (which I have attached) but I then get the following error:

 

  • [Drc 23-20] Rule violation (BIVB-1) Bank IO standard Support - Bank 16 has incompatible IO(s) because: The LVDS I/O standard is not supported. Move the following ports or change their properties: i_SCLK_P

 

I have tried to change to a different bank twice now. I was hoping that I could find a bank with LVDS capability. I have looked through the KC705 datasheet and it appears that the pins that I am using should be valid.

 

Where am I going astray? Thanks for the help!

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Scholar pratham
Scholar
11,783 Views
Registered: ‎06-05-2013

Re: Reading a differential signal into the Kintex 7 KC705

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@tyler.wilson can you consider D26 and C26 MRCC pins for the clock instead of H26 and H27.

 

If you want to use H26 and H27 only you may have to use this in your xdc to bypass the placement error

 

set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets i_SCLK]

-Pratham

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14 Replies
Visitor tyler.wilson
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7,872 Views
Registered: ‎05-08-2015

Re: Reading a differential signal into the Kintex 7 KC705

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I will also say that I am attempting to instantiate an IBUFDS as follows:

 

wire i_SCLK;

 

IBUFDS #(
.CAPACITANCE("DONT_CARE"),
.DIFF_TERM("FALSE"),
.IBUF_DELAY_VALUE("0"),
.IFD_DELAY_VALUE("AUTO"),
.IOSTANDARD("DEFAULT")
) IBUFDS_inst (
.O(i_SCLK),
.I(i_SCLK_P),
.IB(i_SCLK_N)
);

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Scholar pratham
Scholar
7,863 Views
Registered: ‎06-05-2013

Re: Reading a differential signal into the Kintex 7 KC705

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@tyler.wilson bank 16 is HR bank Try LVDS_25 this should work

-Pratham

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Moderator
Moderator
7,860 Views
Registered: ‎01-16-2013

Re: Reading a differential signal into the Kintex 7 KC705

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Hello @tyler.wilson,

 

Which Vivado version are you using? Can you try in Vivado 2015.2

 

Does your design contains MIG core?

Also check if the following thread is helpful:

http://forums.xilinx.com/t5/7-Series-FPGAs/K7-problem-of-HR-BANK-LVDS-signals-selected/m-p/523965

 

--Syed

 

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Visitor tyler.wilson
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7,855 Views
Registered: ‎05-08-2015

Re: Reading a differential signal into the Kintex 7 KC705

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Thank you. I changed my XDC file to say LVDS_25 and now I have a new error:

 

  • [Place 30-574] Poor placement for routing between an IO pin and BUFG. If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .xdc file to demote this message to a WARNING. However, the use of this override is highly discouraged. These examples can be used directly in the .xdc file to override this clock rule. < set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets i_SCLK] > IBUFDS_inst (IBUFDS.O) is locked to IOB_X0Y254 and i_SCLK_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y31

What does this mean?

 

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Visitor tyler.wilson
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7,853 Views
Registered: ‎05-08-2015

Re: Reading a differential signal into the Kintex 7 KC705

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I am using Vivado 2014.2

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Moderator
Moderator
7,850 Views
Registered: ‎01-16-2013

Re: Reading a differential signal into the Kintex 7 KC705

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Hello @tyler.wilson,

 

Can you attach your post synthesis dcp file here?

 

--Syed

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Scholar pratham
Scholar
7,845 Views
Registered: ‎06-05-2013

Re: Reading a differential signal into the Kintex 7 KC705

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@tyler.wilson Look here

 

https://www.google.co.in/search?q=Place+30-574&oq=Place+30-574&aqs=chrome..69i57j69i60&sourceid=chrome&es_sm=93&ie=UTF-8#q=Place+30-574+site:forums.xilinx.com

-Pratham

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Visitor tyler.wilson
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Registered: ‎05-08-2015

Re: Reading a differential signal into the Kintex 7 KC705

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Attached is the dcp file. I hope it was the one that you were looking for

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Visitor tyler.wilson
Visitor
7,812 Views
Registered: ‎05-08-2015

Re: Reading a differential signal into the Kintex 7 KC705

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Also, attached is my top design verilog file.

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Moderator
Moderator
5,666 Views
Registered: ‎01-16-2013

Re: Reading a differential signal into the Kintex 7 KC705

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Hello @tyler.wilson,

 

I get the following CW, when i open the attached dcp file:

CRITICAL WARNING: [Project 1-486] Could not resolve non-primitive black box cell 'clk_wiz_0' instantiated as 'clk_wiz_0' [C:/Users/dmg7145/Documents/Varian_Projects/hdl-hdl_2014_2/projects/fmcomms1_V55_Inputs/kc705/fmcomms1_kc705.srcs/sources_1/new/test0.v:51]
CRITICAL WARNING: [Project 1-486] Could not resolve non-primitive black box cell 'ila_0' instantiated as 'ila_0' [C:/Users/dmg7145/Documents/Varian_Projects/hdl-hdl_2014_2/projects/fmcomms1_V55_Inputs/kc705/fmcomms1_kc705.srcs/sources_1/new/test0.v:59]

 

Can you check this thread and see if it helps:

http://forums.xilinx.com/xlnx/board/crawl_message?board.id=IMPBD&message.id=10157

 

--Syed

---------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.

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Moderator
Moderator
5,664 Views
Registered: ‎07-21-2014

Re: Reading a differential signal into the Kintex 7 KC705

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Hi,

 

From the .dcp file it looks like you are using user IO pins instead of SRCC/MRCC pins.

Please change your design to place clock signal on clock pins.

 

Thanks,
Anusheel
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Scholar pratham
Scholar
11,784 Views
Registered: ‎06-05-2013

Re: Reading a differential signal into the Kintex 7 KC705

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@tyler.wilson can you consider D26 and C26 MRCC pins for the clock instead of H26 and H27.

 

If you want to use H26 and H27 only you may have to use this in your xdc to bypass the placement error

 

set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets i_SCLK]

-Pratham

----------------------------------------------------------------------------------------------
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Visitor tyler.wilson
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5,624 Views
Registered: ‎05-08-2015

Re: Reading a differential signal into the Kintex 7 KC705

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Thanks for the help everyone! It seems to be working great now!

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Visitor tyler.wilson
Visitor
5,547 Views
Registered: ‎05-08-2015

Re: Reading a differential signal into the Kintex 7 KC705

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Some more additional information that might be helpful to more newbie users (like myself). I had multiple input signals that were not clocks but I was using them in always blocks like this:

 

always @(posedge my_signal_name) begin

   blah blah blah;

end

 

I was unaware that when you are trying to trigger on a posedge of a signal in that manner, that it expects the pin to be a clock signal. Hence, I needed to connect my signal to a clock capable pin. So my alternative and fix to my problem was as follows:

 

always @(posedge sys_clk) begin

      if ( my_signal_name == 1) begin

              blah blah blah;

      end

end

 

I  hope that this helps others like me!

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