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Adventurer
Adventurer
4,979 Views
Registered: ‎02-11-2014

Re: Ping --- Reading data from serial 12bit ADC into Kintex-7 --- Ping

jmiles1, you are right.

 

But you have the luck to work with a 16-Bit ADC in two lane mode. It results in 8-Bit per lane, and this is natively supported by Xilinx Core and SerDes.

if you need to interface to a 12-Bit one-lane ADC, things are different. 12-Bit SerDes is NOT natively supported by 7-Series SerDes.

I asked "why?" for several times, but Xilinx refuses an answer. I still can't understand why the 7-series SerDes supports 10-Bit and 14-Bit, but not 12-Bit.

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Contributor
Contributor
4,899 Views
Registered: ‎05-17-2009

Re: Ping --- Reading data from serial 12bit ADC into Kintex-7 --- Ping

Sadly, there are some weird gaps in the coregen IP these days, and they seem to get less flexible over time rather than more flexible. For instance, you (technically) can't create a MIG that can run from a 48 MHz USB clock anymore because they've severely restricted the clocking options. :( A rant from another thread...

What ADC part are you working with?

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Contributor
Contributor
4,869 Views
Registered: ‎03-04-2009

Re: Ping --- Reading data from serial 12bit ADC into Kintex-7 --- Ping

I am using AD9228 from Analog Devices. I am running it at 32MHz sampling clock.

 

I was stupid enough to install Vivado 2015.4 to see if anything had changed to better from 2015.2 and I just got a clock wizard change from vhdl/verilog to verilog only output. Not a big issue as I keep old Vivado releases for this kind of upsets, but it adds to the degenerating flexibility of Vivado. 

Adventurer
Adventurer
4,853 Views
Registered: ‎02-11-2014

Re: Ping --- Reading data from serial 12bit ADC into Kintex-7 --- Ping

Hy,

I'm using AD9637 from Analog Devices.

We run it stable at 50Msps, and are close to achieve stable operation at 75Msps.

 

Regards,

Niels

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Visitor ecorbaley
Visitor
2,231 Views
Registered: ‎08-09-2016

Re: Reading data from serial 12bit ADC into Kintex-7

Hi Niels, 

 

I'm using a ADS5281 it's a 12-bit ADC and I'm running it at 40Msps. I have two master SDR ISERDES, one running with data_p and one with data_n with data_p clocking in the even bits and data_n clocking in the odd bits. The odd bit ISERDES has an inverted bit clock and and I have DYN_CLKDIV_INV_EN and DYN_CLK_INV_EN set to true, but I still have not gotten anything out when I try and run it with hardware. It does not make sense to me to invert the divclk, but I have tried pretty much every combination of DYN_CLKDIV_ EN and DYN_CLK_INV_EN with clocks inverted and noninverted with no results. Do you have both ISERDES blocks with DYN_CLKDIV_EN and DYN_CLK_INV_EN set to true, and do you still invert the CLK in one?

 

Thanks,

EC

   

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Visitor ecorbaley
Visitor
2,216 Views
Registered: ‎08-09-2016

Re: Reading data from serial 12bit ADC into Kintex-7

I found the problem. I was using the lclk from my ADC for both of the ISERDES blocks. This worked in simulation, but did not work on hardware. 

 

Sincerely,

EC

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Visitor bruce_li
Visitor
128 Views
Registered: ‎12-27-2017

Re: Ping --- Reading data from serial 12bit ADC into Kintex-7 --- Ping

Hi, I'm trying to do the saming thing as you. I read the discussion of this thread about XAPP524. It's out of data. Could you please share your design about 12bit lvds ADC with DDR mode? Thank you very much.

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Contributor
Contributor
124 Views
Registered: ‎03-04-2009

Re: Ping --- Reading data from serial 12bit ADC into Kintex-7 --- Ping

The frequency of the DDR data stream must be such that it lies within the adjustment possibilities of the IDELAY element

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