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Adventurer
Adventurer
11,327 Views
Registered: ‎02-11-2014

Reading data from serial 12bit ADC into Kintex-7

Hello all,

 

I have a board with Kintex-7 and AD9637 (Data Sheet atached), and need to read the ADC data into the FPGA.

The AD9637 uses DDR and one differential LVDS data lane per ADC.

 

For 75Msps, this results in a line rate of 900Mbit/second. According to DS182, even the HR pins of a -1 speed grade are able to deal with this data rate.

 

But UG471 implies that the ISERDESE2 element of 7-series FPGAs is not able to deal with 12bit data. I say "implies" because UG471 tells nothing about 12 bit. It just leaves a gap between 10 bit and 14bit.

Then I read XAPP524, and it sounds as if it is possible to read data from a 12bit ADC.

Table 1 in XAPP524 lists

- 12 bit resolution

- 80MHz sample rate

- 1-wire interface

as a valid combination (Comments = OK).

 

Is it possible to read data from a 12bit ADC with 1-wire interface with a Kintex-7?

 

I am looking forward to your answers.

 

Regards,

Niels

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38 Replies
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Adventurer
Adventurer
5,206 Views
Registered: ‎02-11-2014

jmiles1, you are right.

 

But you have the luck to work with a 16-Bit ADC in two lane mode. It results in 8-Bit per lane, and this is natively supported by Xilinx Core and SerDes.

if you need to interface to a 12-Bit one-lane ADC, things are different. 12-Bit SerDes is NOT natively supported by 7-Series SerDes.

I asked "why?" for several times, but Xilinx refuses an answer. I still can't understand why the 7-series SerDes supports 10-Bit and 14-Bit, but not 12-Bit.

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Contributor
Contributor
5,126 Views
Registered: ‎05-17-2009

Sadly, there are some weird gaps in the coregen IP these days, and they seem to get less flexible over time rather than more flexible. For instance, you (technically) can't create a MIG that can run from a 48 MHz USB clock anymore because they've severely restricted the clocking options. :( A rant from another thread...

What ADC part are you working with?

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Contributor
Contributor
5,096 Views
Registered: ‎03-04-2009

I am using AD9228 from Analog Devices. I am running it at 32MHz sampling clock.

 

I was stupid enough to install Vivado 2015.4 to see if anything had changed to better from 2015.2 and I just got a clock wizard change from vhdl/verilog to verilog only output. Not a big issue as I keep old Vivado releases for this kind of upsets, but it adds to the degenerating flexibility of Vivado. 

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Adventurer
Adventurer
5,080 Views
Registered: ‎02-11-2014

Hy,

I'm using AD9637 from Analog Devices.

We run it stable at 50Msps, and are close to achieve stable operation at 75Msps.

 

Regards,

Niels

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Visitor
Visitor
2,459 Views
Registered: ‎08-09-2016

Hi Niels, 

 

I'm using a ADS5281 it's a 12-bit ADC and I'm running it at 40Msps. I have two master SDR ISERDES, one running with data_p and one with data_n with data_p clocking in the even bits and data_n clocking in the odd bits. The odd bit ISERDES has an inverted bit clock and and I have DYN_CLKDIV_INV_EN and DYN_CLK_INV_EN set to true, but I still have not gotten anything out when I try and run it with hardware. It does not make sense to me to invert the divclk, but I have tried pretty much every combination of DYN_CLKDIV_ EN and DYN_CLK_INV_EN with clocks inverted and noninverted with no results. Do you have both ISERDES blocks with DYN_CLKDIV_EN and DYN_CLK_INV_EN set to true, and do you still invert the CLK in one?

 

Thanks,

EC

   

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Visitor
Visitor
2,444 Views
Registered: ‎08-09-2016

I found the problem. I was using the lclk from my ADC for both of the ISERDES blocks. This worked in simulation, but did not work on hardware. 

 

Sincerely,

EC

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Visitor
Visitor
355 Views
Registered: ‎12-27-2017

Hi, I'm trying to do the saming thing as you. I read the discussion of this thread about XAPP524. It's out of data. Could you please share your design about 12bit lvds ADC with DDR mode? Thank you very much.

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Contributor
Contributor
351 Views
Registered: ‎03-04-2009

The frequency of the DDR data stream must be such that it lies within the adjustment possibilities of the IDELAY element

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Participant
Participant
155 Views
Registered: ‎12-18-2017

Thanks @041064974 ,

I had exactly same problem and it was solved thanks to this DYNCLKINVSEL = TRUE and DYNCLKDIVINVSEL = TRUE magic. It probably saved me days of headaches, this was a nasty one.

I happened (at least) with Vivado 2017.4

Thanks!

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