02-01-2019 03:19 AM
I'm writing about a really odd behavior on my implemented design on a ZedBoard board (and Vivado 2017.4).
I designed such a system (very simplified description):
- the FPGA receives a 10 MHz clock from an external source
- the clock feeds a MMCM and generates two different clocks at 100 and 200 MHz (zero phase setting and duty cycle 50%)
- a custom block uses this two clocks to do something like this: assert or deassert four different outputs (say A, B, C and D) depending on the input data.
- The input data is represented by an std_logic_vector(2 downto 0) where bits 2 and 1 are used to set port A and B (if '00' or '11' then A<='0' and B<='0', if '01' then A<='1' and B<='0', if '10' then A<='0' and B<='1') and bit 0 is used to set port C and D (if '0' then C<='1' and D<='0', if '1' then C<='0' and D<='1'). After a clock cycle all the ports are set to '0' and the new set will be done after some clock cycle (set by a dedicated counter).
- The input data vector comes from two different AXI GPIO blocks which are set from dedicated SDK software.
- There are also other blocks which do some stuff using the same 100/200 clock, asserting-deasserting some outputs.
This is what magically happens. The data on the bit0 change the main clocks phase.
Switching between bit0 = '0' and bit0 = '1' introduce a clock shift of about 800 ps. The phase shift is equally applied to both the 100 and the 200 MHz clock, i.e. to all the signals of the design. With a fast change on the bit0 value all the system is crazly bouncing forward and back (+800 ps, - 800 ps)! I measured this phase shift with an oscilloscope looking at the original 10 MHz external clock and an output signal from the FPGA.
I really don't know how this is possibile. I tried to re-generate all the IP-cores or tried with another ZedBoard but nothing changed.
How can a '0' or '1' value act on the MMCM?!?
Thank you very much,
05-29-2019 02:31 AM
does anyone have hints on this topic?
I tried to figure out what could be the reason of this behaviour. Could it be a power supply problem? What happens if the MMCM supply voltage goes below a certain threshold?
05-29-2019 03:16 AM
A schematic of your design or the RTL will help rather than the verbose description.
I also don't understand this bit0 thing which is changing the clock phase.
Cross-check: The input data, 3 bit, is it synced to the 100/200 clock/s?
05-30-2019 08:23 AM
Unfortunately I cannot share the schematic or other information on the design since it is developed under an NDA.
The bit0 is just a bit used as a parameter (set via an AXI GPIO which is in turn controlled via proper software on SDK). The strange behaviour is that if bit0=0 the 100/200 MHz clock have a certain phase (apparantely there are no extra phase added) but when bit0=1 the 100/200 MHz clock get a +800 ps (with respect to the previous phase which I assumed to be zero) on their phase.
The bit0 changing is made "by hand" by the user on the SDK software and the value belongs to the PS clock domain but of course is read by the PL clock domain (the 100/200 clock).
05-30-2019 01:13 PM
The input frequency is set to 10 MHz which is the minimum allowed. It comes from a stable source (quality GPS receiver). The locked signal from the MMCM is high. Furthermore, thanks to a side test I know for sure that even with a 9.9 MHz the MMCM is able to lock to the input frequency.
05-30-2019 02:02 PM
Are you using the variable phase shift feature?
I surmise that is you are using PSCLK, you might be. In which case, the phase shift increment is 1/256 of a full period. Without seeing how the MMCM is instantiated, really cannot help.
06-04-2019 02:00 AM
sorry but I dont' get your answer. What the point of the PSCLK?
06-05-2019 01:00 AM
No I'm not using the Phase Shift.
The MMCM is set to produce one clock at 100 MHz and one at 200 MHz. No phase shift option, i.e. phase=0°.
The clock for the PS is the one coming from the PS IP core itself and is the default one ("Running connection automation" in the block design).