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Observer
Observer
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Registered: ‎02-27-2020

Recommended decoupling capacitors

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Hi

 

A recommended decoupling capacitor quantities of ZU7EV are provided in UG583.

 

Have you ever been faced some issues by having larger capacitance than recommendation?

For instance,  470uF x 5 at VCCINT is too large? but no issues?

 

BestRegards

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Xilinx Employee
Xilinx Employee
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Registered: ‎11-29-2007

Yes they should both work fine. But the officially supported PDN is the one in the UG. It is not recommended to copy the evaluation boards PDNs, as they might have been designed before the UG were published or completed.

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449 Views
Registered: ‎07-23-2019

Rule #1:

More capacitors don't mean better decoupling

Rule #2

Decoupling is not about how many capacitors.

Decoupling means creating a PDN (power distribution network) with an impedance below some level for a range of frequencies.

Adding capacitors adds more than capacitance. Capacitors themselves also have inductance. The board itself adds inductance as well. So you will have resonances (frequencies with high impedance, therefore no decoupling at all). On top of that, because the ultimate goal of decoupling is to have voltages within a range, currents also play a role. That means that even the design in the FPGA is to be taken into account when designing decoupling. I haven't personally noticed it, but in theory, even location of capacitors affects decoupling.

So, forget about "how many". If you find a "magic recipe" about using 3 of these, 8 of those, etc. don't trust it. First of all, not all "0402 100nF 6V3" capacitors are the same in terms of impedance. Even vias location counts. Place vias at the sides of caps instead of straight at the ends and -tadah- you have less added impedance.

Want some advice? (excuse me for advertising the competitor) If you can't access a proper PDN tool like Mentor Graphics hyperlynx, Altera (Intel) had a good decoupling calculator in excel. I wonder if Xilinx has an equivalent thing. 

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Xilinx Employee
Xilinx Employee
448 Views
Registered: ‎11-29-2007
hi,
a small excess in filtering capacitance is generally not a problem.
Do not replace the suggested capacitors with "many" capacitors having higher parasitic L.
Loading the PCB with too much, not needed capacitance is a extra BOM cost and might create problems to power supply at startup.
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440 Views
Registered: ‎07-23-2019

That recommended decoupling list of caps... I don't know how did they get those numbers, honestly. I suppose it's a compromise assuming ten average situations and fifteen typical cases. Will yours be there?

The problem with bad decoupling is that the effect is evil, random and difficult to diagnose. One typically concludes the board misbehaves because of noise, almost out of desperation and after trying and discarding many other things. Once one has been beaten by that, it works like a "vaccine" and engineers tend to be wary of noise and decoupling the rest of their lives.

For "light" boards, small-medium FPGAs, it may work just using that recommended counts. You may have an error now and then but if no one is going to kick your a5s for that, it's okay. But for heavy usage and critical applications, you need a more professional approach.

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436 Views
Registered: ‎07-23-2019

The large caps create a wide dip at the low frequencies and generally don't create resonance problems. But the medium and small ones can do evil things.

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Xilinx Employee
Xilinx Employee
415 Views
Registered: ‎11-29-2007

The prescriptions in the User Guide 583 come from simulations, knowing the device package model.

Extra PCB capacitance does not help too much because of the presence of the device package.

When needed internal capacitors are placed to provide current on demand efficently.

I am confident in UG583 tables. They seem very simple, but there is lot of background analysis from the Package Team. 

A mistake could be to load the PCB with capacitors, maybe trying to balance some PCB lack of solid reference power and GND planes or poor capacitors connections (via+traces) to inner layers. My suggestion is to focus on the quality of the PCB, because the suggested capacitors will be enough.

 

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Observer
Observer
286 Views
Registered: ‎02-27-2020

Hi 

Thank you all.

 

I was just wondering the decoupling capacitors in ZCU106.
This board has 470uF x5, 100uF x4, 4.7uF x3 for VCCINT. 

I had referred ZCU106 and PCU user guide, that's why I had such a question.

As a result, I suppose both of them will be right for proper performance of zynq.  Is it right?

 

 BestRegards

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Xilinx Employee
Xilinx Employee
275 Views
Registered: ‎11-29-2007

Yes they should both work fine. But the officially supported PDN is the one in the UG. It is not recommended to copy the evaluation boards PDNs, as they might have been designed before the UG were published or completed.

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