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parasxos
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Registered: ‎03-04-2017

Recover clock from 8b/10b data stream in FPGA fabric?

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Greetings,

Lets assume a system with 2 FPGAs communicating with each other via an 8b/10b stream at sub 100Mb/s speeds.

Lets call FPGA #1 the master in the sense that it sends an 8b/10b stream with its reference clock and that FPGA #2, the slave, which needs to recover the clock from the the 8b/10b stream in order to use it for its clocking scope.

The question(s): Does the slave FPGA needs a transeiver to recover the clock? Can this be done at those slow speeds in a different way in the FPGA fabric?

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klumsde
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599 Views
Registered: ‎04-18-2011

This is not really possible. 

There is an xapp about asynchronous data transfer over lvds with the selection iserdes. 

It will capture the data stream but it won't give you a recovered clock.

Its not 8b/10b either.

Regards

Keith

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1 Reply
klumsde
Moderator
Moderator
600 Views
Registered: ‎04-18-2011

This is not really possible. 

There is an xapp about asynchronous data transfer over lvds with the selection iserdes. 

It will capture the data stream but it won't give you a recovered clock.

Its not 8b/10b either.

Regards

Keith

-------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------

View solution in original post