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Observer
Observer
7,071 Views
Registered: ‎05-29-2014

Reduced decoupling capacitance for unused IO Banks

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Hello,

 

We have a design with extremely limited PCB size constrains. We are using an Artix 7 family FPGA where there are 2 completely unused I/O banks. According to AR#11906 case is not recommended to leave the BANKs Vcco unconnected because that would lead to reduced ESD protection. Can we bias the unused banks with the regular VCCO voltage but use reduced decoupling capacitance (ex. couple of 100nF per BANK)? Due to PCB space limitations, we want to avoid using bulky capacitors if it's not necessary, so would it be safe to go with just a a couple of 100 nF since these banks will not be driving any loads?

Thanks in addvance.

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Moderator
Moderator
13,324 Views
Registered: ‎07-23-2015

@avon You are welcome. Please close this thread if it answered your query for the benefit of other users

- Giri
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Moderator
Moderator
7,066 Views
Registered: ‎07-23-2015

@avon That should be fine since you are not driving any loads from the Banks and good that you are connecting the unused Bank VCCO pins to a VCCO supply for better ESD protection. 

- Giri
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There's no such thing as a stupid question. Feel free to ask but do a quick search to make sure it ain't already answered.
Keep conversing, give Kudos and Accept Solution when you get one.
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Observer
Observer
7,054 Views
Registered: ‎05-29-2014

Thanks for your quick response. 

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Observer
Observer
7,051 Views
Registered: ‎05-29-2014
Thanks for your quick response.
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Moderator
Moderator
13,325 Views
Registered: ‎07-23-2015

@avon You are welcome. Please close this thread if it answered your query for the benefit of other users

- Giri
--------------------------------------------------------------------------------------------------------------------
There's no such thing as a stupid question. Feel free to ask but do a quick search to make sure it ain't already answered.
Keep conversing, give Kudos and Accept Solution when you get one.
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View solution in original post

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Xilinx Employee
Xilinx Employee
7,044 Views
Registered: ‎08-01-2012

Yes connecting some supply voltage for unused banks VCCO supply rails help to achieve more ESD protection.

Reduced decoupling capacitance for unused IO Banks VCCO supply is also OK. If possible please run Power Integrity (PI) simulations before board fabrication.

 

FYI: Xilinx recommends decoupling capacitors in PCB design user guides based on wide characterization which covers entire operating frequency ranges and full load requirements of that particular FPGA supply rail. Sometimes user may wish to reduce or increase decoupling based on their own application, frequency ranges and board limitations.  In that case user can change decoupling capacitors on their own. Other combinations may work for their specific designs. In that case it is always safe to do power integrity simulations before PCB fabrication.

 

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