Reference clock for GTX's VC7203

[shashankupb]

Hi,

I am using a simple GTX transceiver configuration. For my application I would like to set up a configuration which checks transmitted and recieved bits are same. The clock which is available on the board is 200MHz, I used this clock as a reference clock for my transceivers. In simulation it works fine but, I want to implement this configuration on hardware. The problem I am facing is I can't assign 200MHz on board clock as a reference clock for transceivers.

Am I allowed to do so? If not, what are the other possibilities available?

Is there a fault in setting up configuration (GTX 113-119). which GTX is connected to on board 200MHz clock generator? 

Thank you.

[pulim]

hi @shashankupb

Super clock-2 module provides a programmable clock source for VC7203 board.

Please refer to the board user guide for more details.

http://www.xilinx.com/support/documentation/boards_and_kits/vc7203/ug957-vc7203-gtx-char-board-ug.pdf

And also, you can take the IBERT design as a reference.

http://www.xilinx.com/support/documentation/boards_and_kits/vc7203/2015_1/ug847-vc7203-ibert-gsg-vivado.pdf

[shashankupb]

Hi @pulim Is it not possible to use on board 200MHz clock as a reference clock for MGT's? super clock-2 module generates defaultly 156.25MHz and I tried configuring and running IBERT test, the problem I am facing here is, it is showing in status bar : "no link". I followed the steps in user guide, still its not working for me. Default switch position for glowing APP LED's is working as mentioned in the guide but not with  tx and rx  configuration (Q115). The one thing I noticed during this experience is switch positions mentioned in UG847 are wrong, they should be other way.

And also I am wondering is it possible to generate 200MHz with super clock-2 module because there is no address mentioned for 200MHz in UG847. 

Thank you,

shashank.

[venkata]

It is not possible to use 200MHz clock on the board as input to GT reference clock. Please select a clock frequency available from the table for the super clock-2 module.

From the snapshot, I find the PLLs are not locked. Have you checked if you are connecting the clock input to Si570 (or) Si5368?

Only Si570 provides a default clock of 156.25MHz.

[shashankupb]

Hi @venkata,

I connected clock input to Si570 and also tried with Si5368 still the problem persists. How do I solve this problem now, I also made sure that programmable super clock-2 address is 60 which is for 156.25 MHz.

Thank you.

Best regards,

shashank

[venkata]

Can you check if the bulls eye connectors are loosly connected on the board?

when you set the address to 60, you should press a button below the address entry so that LOL LED on the board will turn off. Do you find this observation?

Please provide the snapshot of the gui when you set the super clock-2 address.

[shashankupb]

Hi @venkata

I fixed bulls eye firmly with elastomer at the bottom and LOL led on board goes off after adding tcl script. I didn't find any press button below the adress entry or do you mean button on board?. But the Alarm LED on board is still on.

[shashankupb]

Hi @venkata @pulim

thanks for your suggestions. I found the solution: UG847 uses wrong notations, I used CLK0 instead of CLK1 which is mentioned on the UG847. Either code is got changed or UG is not updated.

Now I am facing problem with Bit errors for link1. What is the next procedure to make sure that there are no bit errors. There are no errors when I use PRBS7 pattern but when I change it to PRBS31, Link1 is showing bit errors.

And also link rate is not constant to 12.5Gbps, is this might be a problem? what is the importance of TX differential swing?.

Thank you again.

regards 

[venkata]

You can change the differential swing to check the setting which helps to reduce the reflections and ensure proper eye opening at the Rx.