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Visitor gsa
Registered: ‎11-19-2018

Reg. Worst case delay of circuit and Timing constraints for a synchronous circuit

Hey folks,

I am stuck at getting worst case delay to calculate throughput for my circuit that i implemented. can any one you guide me through how to give the values (setup time,holdtime,clktoQ etc) in the constraints file so that i could get nearly accurate worst path dealy.



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1 Reply
Registered: ‎07-18-2018

Re: Reg. Worst case delay of circuit and Timing constraints for a synchronous circuit


   Can you share what the circuit looks like in a general sense (Diagram's are helpful) and what you are trying to report out?

If the circuit is synchronous, you just need to give the clock driving everything a constraint, and it will let you know if it will work, and the values through the path as part of the report.

But if you want to instead put a requirment on how long a path can be, you can use

set_max_delay -datapath

That will instead of doing a normal timing check, will report if the delays from the Clock2Q of the first FF, all the sequential delays, and the final FF are under your requriment. If it fails, you will get a report on the path.

You can also use report_timing_paths and report_timing_arcs to get the path and get_speed_models , and explore the delays if you are curious. But that wouldn't be a check by the tool.

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