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Visitor slacheta
Visitor
630 Views
Registered: ‎01-14-2019

Regarding power off sequencing of Virtex 5 FPGA

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Is there any concern related to device damage or device reliability of Virtex 5 FPGA, if we switch off Vccint first then Vccaux and at last Vcco ? 

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Xilinx Employee
Xilinx Employee
599 Views
Registered: ‎06-06-2018

Re: Regarding power off sequencing of Virtex 5 FPGA

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Hi @slacheta,

FPGA will not get damaged and relaibility is not an issue.

We recommend customers to  follow the power off sequence VCCO,VCCAUX and then VCCINT.

Power sequence is not followed, IO can drive high or low. That behaviour is not documented. 

For your information : The power supplies can be turned on in any sequence,
though the specifications shown in Table 5 are for the
recommended power-on sequence of VCCINT, VCCAUX, and
VCCO. The I/O will remain 3-stated through power-on if the
recommended power-on sequence is followed. Xilinx does
not specify the current or I/O behavior for other power-on
sequences.

For more information please refer page 6 of DS202(v5.5).

Regards,

DEEPAK D N

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2 Replies
Xilinx Employee
Xilinx Employee
600 Views
Registered: ‎06-06-2018

Re: Regarding power off sequencing of Virtex 5 FPGA

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Hi @slacheta,

FPGA will not get damaged and relaibility is not an issue.

We recommend customers to  follow the power off sequence VCCO,VCCAUX and then VCCINT.

Power sequence is not followed, IO can drive high or low. That behaviour is not documented. 

For your information : The power supplies can be turned on in any sequence,
though the specifications shown in Table 5 are for the
recommended power-on sequence of VCCINT, VCCAUX, and
VCCO. The I/O will remain 3-stated through power-on if the
recommended power-on sequence is followed. Xilinx does
not specify the current or I/O behavior for other power-on
sequences.

For more information please refer page 6 of DS202(v5.5).

Regards,

DEEPAK D N

----------------------------------------------------

Please Reply or Give Kudo or Mark it as an Accepted Solution.

-----------------------------------------------------

 

590 Views
Registered: ‎09-17-2018

Re: Regarding power off sequencing of Virtex 5 FPGA

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The question was damage or reliability,

No damage, no reliability concerns as long as abs max voltages are not exceeded.

The behavior of the IO (glitching if sequence not adhered to) is something to consider, which might affect something else in your system.

(As a customer using V5's, this what I was told).