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774 Views
Registered: ‎10-04-2018

Renaming Zynq MIO signals in top-level

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Using Vivado 2018.2, I am trying to split and rename the Zynq processor signals (especially MIO) in the top-level module without success so far.

 

We would like to have custom names according to the interfaces we are using in our board, as we usually do for the PL part. Once the signal names and placement constraints are set, we generate a .csv file that we import in the board design software to generate a custom symbol with the right pin-out of our board.

 

The problem comes during Implementation in Vivado, as the generated XDC file for the PS refers to PACKAGE_PINs with a certain name (MIO...), and therefore Implementation fails. I have tried to disable the XDC file generated with the IP and to include a custom XDC file with the proper naming, however the DCP file generated when synthesizing the IP, still includes the generated constraints.

 

Is there a different way to rename the MIO signals at top-level or disable an automatically generated XDC file that comes with an IP core?

 

Thank you.

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Moderator
Moderator
678 Views
Registered: ‎04-18-2011

Re: Renaming Zynq MIO signals in top-level

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Hi Diego,
I would not persevere with. The MIO are not IO like the FPGA ones. They are not programmed in the bit file the processor sets them up. As such the IO pin planner has no bearing on them. So you can't come along after and try to change how they are set up.
The workaround I suggested should be enough to get a CSV for your schematics.
Putting a wrapper around the PS and trying to change the MIO is not a good idea.
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Moderator
Moderator
748 Views
Registered: ‎04-18-2011

Re: Renaming Zynq MIO signals in top-level

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Hi Diego,

I have not heard of a way to this.

If I open the synthesised design I can't modify the name of the any MIO coming from the PS so they appear as FIXED_IO in the exported CSV. 

 

One workaround I can see is:

In the top level project do "Export IO ports"

Pick XDC. this way you will get the "direction" attribute

 

Take this XDC and Edit it... 

for example replace:

set_property PACKAGE_PIN C12 [get_ports {FIXED_IO_mio[53]}]

with:

set_property PACKAGE_PIN C12 [get_ports my_mio53]

Be sure to change the name everywhere. 

Then create an IO pin planning project in vivado and import the edited xdc into it. 

 

change_mio_name.JPG

 

 

you can now write out the pinout as a CSV. 

 

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687 Views
Registered: ‎10-04-2018

Re: Renaming Zynq MIO signals in top-level

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Thank you for the quick reply. Indeed this is a workaround for generating a CSV file with the proper signal names.

To proceed, I have manually created a wrapper for the Zynq processor converting the inout ports to inputs or outputs when they operate as such (not sure if this is a good idea, though). Then, I generate the XDC automatically with "Export IO ports" and I get the proper names for the MIO signals (as I am doing the manual mapping in the wrapper).

However, when doing Synthesis and Implementation, it still gives many critical warnings when processing the automatically generated XDC file that comes with the Zynq IP core (see attached screenshot). May I just ignore/disable these warnings? Even if I disable the XDC file of the processor, I see them.

As you can see I also get other warnings during synthesis (I guess I can ignore those) and during Place and Route. For the later, I have seen that there are BIDIR buffers automatically inferred in the Zynq processor files, therefore I guess when I map them as outputs Vivado tries to connect both buffers (BIDIR and OBUF) and gives a warning. What would you suggest for these?

Thank you very much again.

Diego

Warnings.png
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Moderator
Moderator
679 Views
Registered: ‎04-18-2011

Re: Renaming Zynq MIO signals in top-level

Jump to solution
Hi Diego,
I would not persevere with. The MIO are not IO like the FPGA ones. They are not programmed in the bit file the processor sets them up. As such the IO pin planner has no bearing on them. So you can't come along after and try to change how they are set up.
The workaround I suggested should be enough to get a CSV for your schematics.
Putting a wrapper around the PS and trying to change the MIO is not a good idea.
-------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------

View solution in original post

663 Views
Registered: ‎10-04-2018

Re: Renaming Zynq MIO signals in top-level

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Ok, I will do so. Thank you again.
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