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Registered: ‎02-08-2018

Reset Asynchronous Assert Synchronous Deassert - why asynchronous assert?

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Why would one want to use a reset synchronizer that will generate an asynchrounous assert when this signal will be used on flip flops (like FDR) with a synchronous reset signal.  I would think if using a FDR, shouldn't the reset synchronizer generate both synchronous assert and deassert?

If the local flip flops were using asynchronous resets like an FDC it would make more sense to me.

Example: Get Smart About Reset: Think Local, Not Global https://www.xilinx.com/support/documentation/white_papers/wp272.pdf

Capture.PNG

The local flip flops shown here are using FDRs, which uses synchronous resets, thus will only reset if the reset is asserted on the rising edge of the clock.  If this is the case, why not just synchronous both the assert (rise) and deassert (fall) of the reset signal?

 Any information would be helpful, thank you.

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Registered: ‎01-23-2009

Re: Reset Asynchronous Assert Synchronous Deassert - why asynchronous assert?

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You are right - if your "local" flip-flops have synchronous set/reset, then there is (almost) no advantage in the asynchronous assertion of the S/R - in fact it is technically a timing violation. That being said, as long as the reset is asserted for more than one clock cycle (and in the case of this diagram it would be, due to the 4 stage reset bridge) the potential violation near the first clock edge of the assertion of reset is harmless - the system will, by definition, cleanly reset on the next cycle.

If you are exclusively using synchronous set/resets, the reset bridge (the 4 back to back FDP) could be replaced with a conventional synchronizer (N back to back flip-flops with the D of one tied to the Q of the previous one). The only disadvantage of this is that the assertion of reset would happen 4-5 clock cycles after the first assertion of the reset input (rather than on the first or second edge of the clock).

The advantage of using a reset bridge here is the avoidance of the above mentioned latency in assertion, and the fact that this synchronized reset can be used in a system that uses both synchronous set/reset and asynchronous preset/clear, with the advantage that the preset/clear will be immediate. And while it is better to use a consistent reset style (preferably all synchronous), there are many designs that use a mixture - for example a design that includes IP with a different reset style, or a design with synchonous resets that has a few flops that must have immediate resets (like motor driver or power FET control signals).

So, since it is harmless to use the reset bridge (and even has some minor advantages) in a pure synchronous system, why not just use it for all systems.

NOTE: In all cases, the N flip-flops of the synchronizer (be they a reset bridge or a conventional N stage synchronizer) must have the ASYNC_REG property set on them.

Avrum

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Guide
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Registered: ‎01-23-2009

Re: Reset Asynchronous Assert Synchronous Deassert - why asynchronous assert?

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You are right - if your "local" flip-flops have synchronous set/reset, then there is (almost) no advantage in the asynchronous assertion of the S/R - in fact it is technically a timing violation. That being said, as long as the reset is asserted for more than one clock cycle (and in the case of this diagram it would be, due to the 4 stage reset bridge) the potential violation near the first clock edge of the assertion of reset is harmless - the system will, by definition, cleanly reset on the next cycle.

If you are exclusively using synchronous set/resets, the reset bridge (the 4 back to back FDP) could be replaced with a conventional synchronizer (N back to back flip-flops with the D of one tied to the Q of the previous one). The only disadvantage of this is that the assertion of reset would happen 4-5 clock cycles after the first assertion of the reset input (rather than on the first or second edge of the clock).

The advantage of using a reset bridge here is the avoidance of the above mentioned latency in assertion, and the fact that this synchronized reset can be used in a system that uses both synchronous set/reset and asynchronous preset/clear, with the advantage that the preset/clear will be immediate. And while it is better to use a consistent reset style (preferably all synchronous), there are many designs that use a mixture - for example a design that includes IP with a different reset style, or a design with synchonous resets that has a few flops that must have immediate resets (like motor driver or power FET control signals).

So, since it is harmless to use the reset bridge (and even has some minor advantages) in a pure synchronous system, why not just use it for all systems.

NOTE: In all cases, the N flip-flops of the synchronizer (be they a reset bridge or a conventional N stage synchronizer) must have the ASYNC_REG property set on them.

Avrum

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Registered: ‎02-08-2018

Re: Reset Asynchronous Assert Synchronous Deassert - why asynchronous assert?

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Thank you Avrum for sharing the cons and pros of why having this reset bridge in place makes sense. You have an awesome Holiday!!
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