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Visitor
Visitor
540 Views
Registered: ‎08-08-2019

Rising and Falling edge error

hi

I do not simulate

I want to lick both the rising and failing edge of the 1 entry How can I do this I'd try

if Signal_in'event and Signal_in='1' then

i <= i + 1;

elsif Signal_in2'event and Signal_in2='0' then

i <= i + 1;

end if;

if Signal_in'event then if Signal_in = '1' and edge_state=false then i <= i + 1;

edge_state <= true; elsif Signal_in = '0' and edge_state=true then i <= i + 1;

edge_state <= false;

end if;

end if;

not works

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3 Replies
Highlighted
517 Views
Registered: ‎06-21-2017

First, "not works" is a poor description of your problem.  Do you get an error message?  Is it a syntax check error, a synthesis error or an Implementation error?  What is the error message and what line in your code does it reference?

The only registers in a Xilinx FPGA that can respond to both the rising edge and falling edge of a clock are in the Input/Output tiles.  Registers inside the FPGA can only respond to one edge of a clock. 

Your code has multiple registers driving the signal "i".  Only one register output may drive a signal.

Are Signal_in and Signal_in2 really clocks (constantly running periodic signals) or are they something else?  Using a regular signal as the clock input to a register is very bad design practice.

Highlighted
Teacher
Teacher
512 Views
Registered: ‎07-09-2009

A few other comments

 

welcome to the world of VHDL.

You will love and hate the strict constraints, stick with it its worth it.

String suggestions

a) Dont use Signal_in'event and Signal_in='1'  , use if rising_edge( signal_in )

b) make certin this is inside a process with the correct sensetiity list

c) Always simulate...  Simulatoin is quicker than synthesis and tells you a lot more about your circuit . You will spend may be 60 % of your life simulating, 30 % designing, and 10 percent waiting for synthesis.

d) always rember that your code is describing hardware, if you can't think what the hardware is , the its likely the tools can not either.

( and yes there are no DDR flip flops in the FPGA )

Why do yo u want  DDR internal flipflops ?

 

 

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
Highlighted
Scholar
Scholar
486 Views
Registered: ‎08-07-2014

@trnkttc,

if Signal_in'event and Signal_in='1' then

i <= i + 1;

elsif Signal_in2'event and Signal_in2='0' then

i <= i + 1;

end if;

Not possible to do within the FPGA.

Pay attention to what others have said above.

 

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FPGA enthusiast!
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