06-17-2016 01:39 PM
I've a quick clarification. I'm using a AC701 Eval Board with the Artix 7 Series FPGA to route an input clock (10MHz Freq) into the device.
I'm using the PIN D18 (which is a SRCC CCIO P end of differential pair) to accept my input clock, and I've constrained only the P side in my XDC file. I've routed the pin in my RTL via a IBUFG.
My question is: Can I use the PIN C18 (which is the N end of the same above used pair) for my data or should I leave it unconnected?
06-17-2016 05:39 PM
As with any differential pair of pins, they can either be used together as a differential pair, or separately as two independent single ended signals. The clock capable diff pair is no different - if you use the P side as a single ended clock input, then the N side is available to use as a single ended data signal.
Of course, the N side of the clock capable differential pair CANNOT be used for a second single ended clock - there is no dedicated internal route from the N side of the differential pair to the clock resources in the FPGA. (To be clear) the N side of a CCIO is not a clock capable pin.