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Observer
Observer
853 Views
Registered: ‎10-27-2017

Running a 7z007S without external RAM (power estimator shows 1W power usage from RAM alone???)

Hi All,

 

I'm trying to figure out if I can use the zynq family in a project. One of my main concerns is power usage.

The design will run several zynq devices on USB power alone. 

Only one of the devices actually needs RAM. The other (a maximum of 3 devices) can be run without any external memory whatsoever. A very simple programming running on the one cortex A9, possible at highly reduced clockspeed for some slow GPIO.

The artix 7 inside will do the most of the work.

 

When playing with xilinx power estimation tool a WHOPPING 1W can be saved when going from a design with DDR (medium to high resources usage on all other subsystems) to a design without RAM (with the same usage on all but the DDR subsystem).

The quick estimate feature shows a power usage that goes from about 1.3 W to 0.255W.

 

Is this just a quirk of the power estimation tool or can you really get a zynq with a non trivial FPGA load running at these low power targets?

 

The one device that needs RAM...can you save significantly going to slower RAM like DDR2 running at slower speeds or is that too a quirk of the tool?

 

 

A BIG thanks for all helpful!

 

 

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Explorer
Explorer
799 Views
Registered: ‎05-25-2016

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Observer
Observer
786 Views
Registered: ‎10-27-2017

Thanks! I'll try to get this working on a 7z007 board and see what power savings can be had from skipping DDR all together!
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Observer
Observer
733 Views
Registered: ‎10-27-2017

I tried the solution that's described in

https://wiki.trenz-electronic.de/display/PD/DDR+less+ZYNQ+Design

but couldn't get it to work on a minizedboard in vivado 2018.

 

The hacked FSBL seems to run and write the bitstream to the FPGA but the fpga doesn't do a thing.

 

I loaded two counters in it...one clocked form the ps PLL side and one clocked by an external signal generator but both stay completely quite after being programmed. 

 

When I program with JTAG they start up like they should.

 

Is there something keeping the PL side on inactive? What could that be? 

Or is the bitstream programming just not working like it should.

 

I don't know how to check this.

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Xilinx Employee
Xilinx Employee
683 Views
Registered: ‎06-30-2010

regarding the DDR power query, XPE is very accurate and so what you are seeing is correct. Things like slowing the interface down can have a larger impact on the power consumed.
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