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Visitor volta
Visitor
1,750 Views
Registered: ‎08-05-2016

SLICES and carry

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Hi,

 

I have recently instantiated the CARRY4 primitive, and I see there are two carry inputs, CYINIT and CI.

 

As far as I know, CARRY4 should only need one input for the carry of the previous CARRY4, and I think this is the function of the CI input, therefore I don´t really understand what is the function of CYINIT, it seems a redundant input.

 

What is the real difference between CYNIT and CI?

 

Thank you very much

 

Volta

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Moderator
Moderator
2,180 Views
Registered: ‎09-18-2014

Re: SLICES and carry

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volta,

 

The simple answer to your initial question on what the difference between CI and CYINIT is that CI is strictly used for cascading inputs from another CARRY output of a different SLICE. So it's usually used when you have CARRY chains when a single CARRY BLOCK is not enough. CYINIT is used for the rest of the cases including the first/upper CARRY input in the chain. It is the initial CARRY bit or first bit in the CARRY chain. For example, if you want to initialize a CARRY input to be a static 0 or 1 you would use CYINIT. Just a word of advice why don't you just create a simple 16-bit or 31-bit adder using our adder/subtractor IP/wizard and see post synth or implementation results of how the CARRY blocks are connected and how CYINIT and CI inputs are used. I also recommend reading some digital logic books into how lookahead carry logic works. There is usually always a C0 initial input to the carry logic. That C0 in this scenario is depicted by CYINIT. 

 

A quick example below you can see CYINIT is hard tied the upper/first CARRY input to 0 by just grounding it. CYINIT can be a hard value or could be variable but it needs to be known at the CYINIT input of the CARRY block. It does NOT depend on DI and S... CI DOES!  In this chain, CI on the first CARRY block is grounded because the first CARRY block does not use it! The rest of the CARRY blocks do use CI and do not use CYINIT.

adder_CARRY4.JPG

 

Regards,

T

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Xilinx Employee
Xilinx Employee
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Registered: ‎08-01-2008

Re: SLICES and carry

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For the first CARRY4 instance in a chain, the CYINIT is used to determine the add/subtract functionality.
The carry chain runs upward and has a height of eight bits per CLB slice. The carry initialize input CYINIT is used to select the first bit in a carry chain. The value for this input is either 0  (for add), 1  (for subtract), or AX input (for  the dynamic first carry bit).

The CI and CYINIT have the following correct connections:

CI <= GND
CYINIT <= VCC

 

REQP-1745#1 Advisory
connects_CI_VCC_connects_CYINIT_GND
The CARRY4 cell
top/sub1/sub2/test_reg_i_3
has CI tied to VCC and CYINIT tied to GND. The CYINIT connection to GND will take precedence.

Thanks and Regards
Balkrishan
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Visitor volta
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Registered: ‎08-05-2016

Re: SLICES and carry

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Hi @balkris,

 

It is a very interesting point; I know that there is one CARRY4 per SLICE so I suppose there is two SLICEs per CLB.

 

If the CYINIT is used to select the first bit in a carry chain then I understand that in a chain, all the CARRY4 will be connected using the CI input except the first one which must use the CYINIT input.

 

I wonder if this is how it really works, because I am a little confused at the moment.

 

Thanks

 

Volta.

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Moderator
Moderator
2,181 Views
Registered: ‎09-18-2014

Re: SLICES and carry

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volta,

 

The simple answer to your initial question on what the difference between CI and CYINIT is that CI is strictly used for cascading inputs from another CARRY output of a different SLICE. So it's usually used when you have CARRY chains when a single CARRY BLOCK is not enough. CYINIT is used for the rest of the cases including the first/upper CARRY input in the chain. It is the initial CARRY bit or first bit in the CARRY chain. For example, if you want to initialize a CARRY input to be a static 0 or 1 you would use CYINIT. Just a word of advice why don't you just create a simple 16-bit or 31-bit adder using our adder/subtractor IP/wizard and see post synth or implementation results of how the CARRY blocks are connected and how CYINIT and CI inputs are used. I also recommend reading some digital logic books into how lookahead carry logic works. There is usually always a C0 initial input to the carry logic. That C0 in this scenario is depicted by CYINIT. 

 

A quick example below you can see CYINIT is hard tied the upper/first CARRY input to 0 by just grounding it. CYINIT can be a hard value or could be variable but it needs to be known at the CYINIT input of the CARRY block. It does NOT depend on DI and S... CI DOES!  In this chain, CI on the first CARRY block is grounded because the first CARRY block does not use it! The rest of the CARRY blocks do use CI and do not use CYINIT.

adder_CARRY4.JPG

 

Regards,

T

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Visitor volta
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1,613 Views
Registered: ‎08-05-2016

Re: SLICES and carry

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@tenzinc

 

Thank you very much for your explanation, the concept is now clear.

 

I am going to follow your advice and play a little with the adder/substractor IP wizard and the post implementation results; I want to fully understand how the CARRY4 works.

 

Just a last question, I understand the CARRY4 has his own route inside the FPGA, so I suppose maybe the CYINIT is receiving the carry from the standard data route while the CI receive the carry from the private route of the CARRY4.

 

Thanks again,

Volta.

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