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Bruno68
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Registered: ‎12-09-2020

SP701 spartan 7 - Internal clock using through SI570BAB000875DG

We are using SP701 for a spartan 7 xc7s100fgga676-1 evaluation Kit.

We would like to use the component Silicon Labs SI570BAB000875DG embedded on the board.

We know that this component generate by default a 33 MHz clock.

Currently, we try to observe this clock divided by 1000.

As you can see, we have instantiated IBUFDS

 

Bruno68_0-1618822320293.png

 

and the constraint file is :

 

Bruno68_1-1618822320302.png

 

Unfortunately, we can't manage to observe the clock divided.

Is someone has a solution?

Thank you in advance

Best Regards

 

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bruce_karaffa
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Scholar
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Registered: ‎06-21-2017

How are you trying to observe the output, an oscilloscope?  What do you see?  As an aside, if you post your code using the Insert/edit Code icon </>  the code will be more readable than a screenshot.

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Bruno68
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Registered: ‎12-09-2020

Hello,

Finally, we manage to observe the clock divided by 200. Input signal level was 2.5V instead of 3.3V.

But I notice that the frequency of the output is 1MHz that means that the default frequency of the component  SI570BAB000875DG is 200MHz and not 33MHz.

Have you ever seen this ?

Here below, constraint file :

 

set_property LOC AE8 [get_ports input_p]
#set_property PACKAGE PIN AE8 [get_ports input_p]
set_property IOSTANDARD LVDS_25 [get_ports input_p]
set_property DIFF_TERM TRUE [get_ports input_p]

set_property LOC AE7 [get_ports input_n]
#set_property PACKAGE PIN AE7 [get_ports input_n]
set_property IOSTANDARD LVDS_25 [get_ports input_n]
set_property DIFF_TERM TRUE [get_ports input_n]

set_property LOC E11 [get_ports output_1]
#set_property PACKAGE PIN E11 [get_ports output_1]
set_property IOSTANDARD LVCMOS18 [get_ports output_1]


set_property LOC E6 [get_ports LogresL]
set_property IOSTANDARD LVCMOS18 [get_ports LogresL]

set_property LOC M7 [get_ports LogresL_out]
set_property IOSTANDARD LVCMOS18 [get_ports LogresL_out]

 

 

Here below, vhdl code :

 

 

LIBRARY ieee;
USE IEEE.std_logic_1164.ALL;
USE IEEE.std_logic_unsigned.ALL;

--LIBRARY LIB_PROTO;
--USE LIB_PROTO.pack_proto_top.ALL;

library UNISIM;
use UNISIM.vcomponents.all;


ENTITY proto_charge_top IS
PORT (
         LogresL         : IN STD_LOGIC;
         --CLOCKS
         input_p         : IN  STD_LOGIC;
         input_n         : IN  STD_LOGIC;
         LogresL_out     : OUT STD_LOGIC;
         output_1        : OUT std_logic
     );
END proto_charge_top;

ARCHITECTURE rtl OF proto_charge_top IS

SIGNAL cpt          : std_logic_vector(7 downto 0);
SIGNAL output_1_loc : std_logic;
SIGNAL Clock        : std_logic;
CONSTANT CST_100    : std_logic_vector(7 downto 0):="01100100";
CONSTANT CST_1      : std_logic_vector(7 downto 0):="00000001";

BEGIN

output_1    <= output_1_loc;
LogresL_out <= LogresL;

IBUFDS_inst : IBUFDS
generic map (
     diff_term => true,
     ibuf_low_pwr => true,
     iostandard => "default"
            )
PORT MAP (
      O => Clock,
      I => input_p,
      IB => input_n
        );

PROCESS(LogresL, Clock)
BEGIN
  IF LogresL = '0' THEN
    cpt          <= (OTHERS => '0');
    output_1_loc <= '1';
  ELSIF rising_edge(Clock) THEN
    cpt <= cpt + "01";
    IF cpt = CST_100 THEN
      output_1_loc <= not(output_1_loc);
      cpt <=  CST_1;
    END IF;
  END IF;
END PROCESS;

END rtl;
                                

 

Best Regards

Bruno.

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