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Participant
Participant
941 Views
Registered: ‎12-07-2008

SPARTAN6 LVDS DDR data capture

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hi,

  I am now trying to capture the output data from an ADC. The ADC acceptes a main clk from the FPGA (10MHz), and outputs a frame clk (10MHz), a Data_bit clk (80MHz), and a Dout (16bits serial, MSB first, DDR, syncronized to Data_bit clk).

 I use IDDR2 as the interface to the ADC:

   IDDR2_inst_0 : IDDR2
   generic map(
      DDR_ALIGNMENT => "C0", -- Sets output alignment to "NONE", "C0", "C1" 
      INIT_Q0 => '0', -- Sets initial state of the Q0 output to '0' or '1'
      INIT_Q1 => '0', -- Sets initial state of the Q1 output to '0' or '1'
      SRTYPE => "SYNC") -- Specifies "SYNC" or "ASYNC" set/reset
   port map (
      Q0 => s_data_reg0(0), -- 1-bit output captured with C0 clock
      Q1 => s_data_tmp0(0), -- 1-bit output captured with C1 clock
      C0 => s_clk, -- Data_bit clk
      C1 => s_clk_n, -- (not) Data_bit clk
      CE => '1',  -- 1-bit clock enable input
      D => P_I_DIN(0),   -- Dout
      R => s_rst,    -- 1-bit reset input
      S => '0'     -- 1-bit set input
   );	

and this is followed by a shift register, so that i can get a 16 bit parallel data every 8 bit clks.

I have problem in syncronizing DOUT to Frame clk.

from the ADC datasheet, dout is syncronized to the rising edge of the frame clk, so I guess if I can capture rising edge of the frame clk, I can know exactlly when is the start of a new sampled data.

 

What I am doing now is that I register frame clk:

                                           f_clk_reg0 <= f_clk_reg <= f_clk

at each rising edge of data_bit_clk, and then use the following condition to see if it is an rising edge of f_clk (and put start_en high if so)

                                          f_clk_reg0  = '0' and f_clk_reg  = '1'

it seems a pretty simple logic, but dosen't work, looks like start_en goes high at ramdon places....

 

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Participant
Participant
908 Views
Registered: ‎12-07-2008

problem soloved!

The ADC that i use has a default SERIALIZED_DATA_RATE of 14 bit, and in this case DCLK = 7 * FCLK.

Instead of conducting the FCLK and DCLK synconization procedure imidiately after reset, I have to wait for some time, till I have finished configurating the ADC, so that SERIALIZED_DATA_RATE is 16 and DCLK = 8 * FCLK.

View solution in original post

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Participant
Participant
909 Views
Registered: ‎12-07-2008

problem soloved!

The ADC that i use has a default SERIALIZED_DATA_RATE of 14 bit, and in this case DCLK = 7 * FCLK.

Instead of conducting the FCLK and DCLK synconization procedure imidiately after reset, I have to wait for some time, till I have finished configurating the ADC, so that SERIALIZED_DATA_RATE is 16 and DCLK = 8 * FCLK.

View solution in original post

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Xilinx Employee
Xilinx Employee
898 Views
Registered: ‎06-30-2010
great! please mark your own answer as accepted solution :)
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