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ronnywebers
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Registered: ‎10-10-2014

STARTUPE2 - use case examples

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I just came accross the STARTUPE2 primitive, and I'm wondering what it is typically used for? Can someone shed a more high-level view on the use cases of this primitive? When do you need it / use it?

 

 

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chapman
Xilinx Employee
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Registered: ‎09-05-2007

When and SPI Flash is used to configure the device the configuration image doesn't completely fill all of the Flash memory. Therefore, there is some spare non-volatile memory that the design can access to store some useful data. I have provided a PicoBlaze reference design that it implements the SPI Master signalling and the slave protocol that can access an SPI Flash device in less than 30 Slices.

 

https://www.xilinx.com/products/intellectual-property/picoblaze.html

 

See 'design Files' tab and download the 'KCPSM6' package. In the zip file you will find a 'Reference Designs' folder containing an  'SPI' folder where this reference design that used the STARTUPE2 primitive is provided and documented.

 

Another reason to access the Flash after configuration is to be able to update a configuration image. The 'MultiBoot' scheme is one in which you store more than one image in the Flash memory. The normal situation is to have a 'golden' image stored starting at address zero which is a default design which has the ability to perform a remote upgrade of the second image in Flash and then reboot the device with that image.

 

 

 

Ken Chapman
Principal Engineer, Xilinx UK

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zhendon
Community Manager
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Registered: ‎08-30-2011

Hi

 

You may find detail information in configuration user guide UG470 for this primitive.

The general usage of this primitive is to use control configuratioin dedicated pin (like CCLK for 7 series ) post configuration.

Configuration dedicated pin cannot be directly controlled after configuration, but in some scenario, it needs to access the external SPI flash which is used to store FPGA configuration bit file.

 

Below is the example to instantiate the primitive in your design.

STARTUPE2_​INST: STARTUPE2

generic map(

PROG_​USR => "FALSE",​

SIM_​CCLK_​FREQ => 0.0)

port map (

CFGCLK => open,​

CFGMCLK => open,​

EOS => open,​

PREQ => open,​

CLK => '0',​

GSR => '0',​

GTS => '0',​

KEYCLEARB => '0',​

PACK => '0',​

USRCCLKO => spi_​clk,​ -- external (EMCCLK) spi_​clk signal from the design which is provide signal to output on CCLK pin USRCCLKTS => '0',​ -- Enable CCLK pin

USRDONEO => '1',​ -- Drive DONE pin High even though tri-state USRDONETS => '1' );​ -- Maintain tri-state of DONE pin

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ronnywebers
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Registered: ‎10-10-2014

thanks - I'm currently using Zynq, not sure if the STARTUPE2 has any use there (?)

 

why would a device want to access the SPI config flash after it is configured? To load another config? Or some user data? Or a bitstream for a partial reconfig? Just really curious :-)

 

 

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chapman
Xilinx Employee
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Registered: ‎09-05-2007

When and SPI Flash is used to configure the device the configuration image doesn't completely fill all of the Flash memory. Therefore, there is some spare non-volatile memory that the design can access to store some useful data. I have provided a PicoBlaze reference design that it implements the SPI Master signalling and the slave protocol that can access an SPI Flash device in less than 30 Slices.

 

https://www.xilinx.com/products/intellectual-property/picoblaze.html

 

See 'design Files' tab and download the 'KCPSM6' package. In the zip file you will find a 'Reference Designs' folder containing an  'SPI' folder where this reference design that used the STARTUPE2 primitive is provided and documented.

 

Another reason to access the Flash after configuration is to be able to update a configuration image. The 'MultiBoot' scheme is one in which you store more than one image in the Flash memory. The normal situation is to have a 'golden' image stored starting at address zero which is a default design which has the ability to perform a remote upgrade of the second image in Flash and then reboot the device with that image.

 

 

 

Ken Chapman
Principal Engineer, Xilinx UK

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ronnywebers
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thanks @chapman, that sheds some more light :-)

 

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htong1
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Registered: ‎05-13-2019

Hi, In Chapman's reference design, the Microblaze is directly connected to the MOSI and MISO for the configuration SPI flash. I have two questions:

1. How does the FPGA configuration from the SPI flash work? Is the MISO still implicitly connected to the JTAG configuration controller even though in the reference design the MISO is directly connected to the Microblaze?

2. How does the JTAG programming bitstream to the configuration SPI flash thru FPGA work? Does the JTAG programming thru FPGA has another implicit path to bypass the direct connection between the Microblaze and the MOSI?

Would anyone help to explain how it works?

Thanks

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allanherriman
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Registered: ‎01-08-2012

I mostly use it so that I can access CFGMCLK.  Sometimes I need a reliable clock inside the FPGA fabric, for example if I want to test external crystal oscillators during production tests.

(That's reliable in the sense that I know it oscillates if the FPGA configures.  The jitter, accuracy and stability aren't that great.)

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