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Observer
Observer
12,533 Views
Registered: ‎07-02-2013

STARTUPE2 with SPI FLASH Programming

I would like to use the CCLK after configuration, to burn the SPI flash with a new program file.

Does anyone know how exactly I should connect the STARTUPE2 primitive?

 

I attached my instance, that received the “MY_CLK” input, BUT on simulation or on the LAB, I don’t see the CCLK moving…

 

Thanks,

 

 

STARTUPE2 #(

                       .PROG_USR("FALSE"),    

                       .SIM_CCLK_FREQ(10.0))

     STARTUPE2_inst (

                                     .CFGCLK      (/* NC */),

                                     .CFGMCLK  (/* NC */),

                                     .EOS             (/* NC */),

                                     .PREQ          (/* NC */),

                                     .CLK      (1'b0),

                                     .GSR      (1'b0),

                                     .GTS      (1'b0),

                                     .KEYCLEARB(1'b0),

                                     .PACK     (1'b0),

                                     .USRCCLKO (MY_CLK),

                                     .USRCCLKTS(1'b1),

                                     .USRDONEO (1'b0),

                                     .USRDONETS(1'b0) 

                                     );

 

 

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Community Manager
Community Manager
12,522 Views
Registered: ‎07-23-2012

Refer to http://www.xilinx.com/support/documentation/application_notes/xapp1020.pdf

You can use this as a reference to build your design.
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Xilinx Employee
Xilinx Employee
12,521 Views
Registered: ‎10-11-2007

For one, the USRCCLKTS must be driven low to enable the CCLK output..

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Observer
Observer
12,511 Views
Registered: ‎07-02-2013

Hi All,

 

Still it’s NOT working…

I connected the USRCCLKTS to 1’b0 and insert a free run clock (just for testing) of 30MHz to the USRCCLKO, but I don’t see any clock on the Lab with the scope… (on the SPI Flash).

I am working with Kintex160 on VIVADO software.

Maybe I need to add some constrain on the XDC file that related to STARTUPE2..? (something like set_property …) ?

 

Thanks for your help.

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Observer
Observer
12,500 Views
Registered: ‎07-02-2013

hi,

 

Still dont work...

Maybe i need to add some configuration on the XDC like

BITSTREAM.STARTUP..... etc'

 

thanks,

 

 

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Xilinx Employee
Xilinx Employee
12,490 Views
Registered: ‎10-11-2007

No bitstream options or constraints required. Your "my_clk" should come out on the CCLK pin now.

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Observer
Observer
12,477 Views
Registered: ‎07-02-2013

I found that the STARTUPE2 module is deleted by the synplify_pro syntesis...

 

"Pruning instance STARTUPE2_inst -- not in use ..."

 

I need to search for some constrint, that will prevent the software to delete it...

 

 

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Community Manager
Community Manager
12,464 Views
Registered: ‎07-23-2012

You can use (*keep="TRUE"*) in Verilog. For more information on this constraint, please refer to page 135 of http://www.xilinx.com/support/documentation/sw_manuals/xilinx13_4/cgd.pdf
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Observer
Observer
12,460 Views
Registered: ‎07-02-2013

 

O.K it works now J BUT,

1. I need to connect one of the STARTUPE2 outputs to some port… otherwise the Synplify synthesis delete the STARTUPE2 module. I need to find some constraint that is valid for Synplify software.

2. I have problem in simulation. If the GSR is connected to zero, then the OSERDES that I have also in my design is started to output XXX (RED) and pass to good data only after some time when the reset is released. If I remove the STARTUPE2 from the design, then the OSERDES worked fine from the beginning.

 

thanks for your help!

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Observer
Observer
12,454 Views
Registered: ‎07-02-2013

For Synplify we should add:

/* synthesis syn_noprune = 1 */

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