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Registered: ‎02-03-2016

Save User Data on SPI Flash

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I have a Basys 3 Board (with XC7A35 FPGA and a SPI Flash Memory S25FL032).  I want to write a VHDL project that saves and reads application Data to Flash Memory. The Flash Memory uses configuration Pins of the FPGA so I've read that the Startupe2 primitive has to be used to access to SPI Flash Pins. There are some manuals that describe the process but I am looking for a detailt describtion and a reference project (with vhd-file(s) and xdc-file)

Thanks in advance for your help

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Community Manager
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Registered: ‎07-23-2012
You can make use of AXI Quad SPI IP for meeting your requirement.

You may refer to the PG153/example design of the IP for more guidance.
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Thank you for your response. The information you have sent is very interesting, but unfortunately I haven’t found what I’m looking for. I don't want to use the internal Block Ram for saving data, I want to use the nonvolatile external SPI flash memory. The program for the FPGA is stored in the SPI flash memory. The memory is much bigger than needed for the FPGA Program so the user can use a part of the memory to save data. In the thread and in the project, I haven't found information writing to SPI flash or reading from it. To use the SPI flash there has to be constraints in the XDC file. These constraints are included in the master XDC of the Basys3 board. Here you can find this part of the master XDC file.


##Quad SPI Flash

##Note that CCLK_0 cannot be placed in 7 series devices. You can access it using the

##STARTUPE2 primitive.

#set_property PACKAGE_PIN D18 [get_ports {QspiDB[0]}]                                                     

                #set_property IOSTANDARD LVCMOS33 [get_ports {QspiDB[0]}]

#set_property PACKAGE_PIN D19 [get_ports {QspiDB[1]}]                                                     

                #set_property IOSTANDARD LVCMOS33 [get_ports {QspiDB[1]}]

#set_property PACKAGE_PIN G18 [get_ports {QspiDB[2]}]                                                     

                #set_property IOSTANDARD LVCMOS33 [get_ports {QspiDB[2]}]

#set_property PACKAGE_PIN F18 [get_ports {QspiDB[3]}]                                                      

                #set_property IOSTANDARD LVCMOS33 [get_ports {QspiDB[3]}]

#set_property PACKAGE_PIN K19 [get_ports QspiCSn]                                                                            

                #set_property IOSTANDARD LVCMOS33 [get_ports QspiCSn]

 

Above the declaration of the pins you find the information that CCLK is no user IO and this port cannot be placed in the 7 series devices. Without a clock on the CCLK pin of the SPI-flash I can neither write to the memory nor read from it. To set the clock for the memory I have to use the startupe2 primitive. There is a code example using the startupe2 primitive to set a clock for the flash memory. That’s why I’m looking for an easy code example (vhd file matching to the constraints in the xdc file above) that realizes the signals you can find in the datasheet of the flash on page 24 and 41 (https://www.spansion.com/Support/Datasheets/S25FL032P_00.pdf). I amlooking forward to your answer and thanking you in advance

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Community Manager
Community Manager
21,525 Views
Registered: ‎07-23-2012
You can make use of AXI Quad SPI IP for meeting your requirement.

You may refer to the PG153/example design of the IP for more guidance.
-----------------------------------------------------------------------------------------------
Please mark the post as "Accept as solution" if the information provided answers your query/resolves your issue.

Give Kudos to a post which you think is helpful.

View solution in original post