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immi4net
Observer
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Registered: ‎06-24-2011

SelectIO output bus width of ISERDES

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Hi,

I am trying to interface the Low speed 4MSPS ADC differential interface to ZYNQ device. 

The IQ data is serial interleaved 16bit I then 16 bit q build the 32 bit serialization on double data rate.

I want to use SelectIO wizerd for the ISERDES configuration, but the maximum output bus width can be achieved upto 14bits .

 

How can i use the ISERDES in cascade mode to acheive the 32 bit deserialization.

 

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LawsonSSEC
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Registered: ‎06-03-2016

As far as I can tell, the ISERDES is designed to bridge the gap between the maximum speed of the IO pins and the speed at which most logic designs run.  I.e. de-serialise a ~1Gbps data stream enough so that logic running at 100-250MHz can deal with it.  So ratios of 1:4 or 1:7 and one stage of cascading is sufficient.  From that point on, programmable logic can do the rest.

 

In your case, I'd run the ISERDES at 1:8 and code a shift register to do 8:32 buss width expansion.  128MBps is also slow enough that you could just code a 1:32 shift register yourself and completely avoid the SelectIO wizard.  That said, I'd be really nice if the SelectIO wizard would add extra width extension logic automatically and have the option to setup a PLL to clock it all.

 

Marty

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athandr
Xilinx Employee
Xilinx Employee
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Registered: ‎07-31-2012
Hi,

Please note that the the ISERDES cascade mode can be only used upto 2 ISERDES and thus max of 14 parallel bits. You cannnot go further than that. If you want further de-serialization you need to go for the Gigabit transceivers.

Please check pg155 of the below link about the ISERDES CASCADE information.

http://www.xilinx.com/support/documentation/user_guides/ug471_7Series_SelectIO.pdf
Thanks,
Anirudh

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immi4net
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Registered: ‎06-24-2011

Thanx,

How can i capture in such case the ADC samples, my clock and data is source synchronous but its Double data rate?

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immi4net
Observer
Observer
5,205 Views
Registered: ‎06-24-2011

can i use an IDDR block using selectIO wizard. After this block i convert the serial bits into parallel bus?

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LawsonSSEC
Visitor
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9,565 Views
Registered: ‎06-03-2016

As far as I can tell, the ISERDES is designed to bridge the gap between the maximum speed of the IO pins and the speed at which most logic designs run.  I.e. de-serialise a ~1Gbps data stream enough so that logic running at 100-250MHz can deal with it.  So ratios of 1:4 or 1:7 and one stage of cascading is sufficient.  From that point on, programmable logic can do the rest.

 

In your case, I'd run the ISERDES at 1:8 and code a shift register to do 8:32 buss width expansion.  128MBps is also slow enough that you could just code a 1:32 shift register yourself and completely avoid the SelectIO wizard.  That said, I'd be really nice if the SelectIO wizard would add extra width extension logic automatically and have the option to setup a PLL to clock it all.

 

Marty

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immi4net
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Registered: ‎06-24-2011

Thanx Marty for your time,

 

"In your case, I'd run the ISERDES at 1:8 and code a shift register to do 8:32 buss width expansion."

 

I think this would be the more appropriate as Select IO can handle the differential clock to single ended and differential LVDS data to single ended, also handling the data on ddr rate adds the BUFGs etc.

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