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Contributor
Contributor
751 Views
Registered: ‎08-30-2018

SelectIO with delay

I am interfacing a xc7z045fbg (speedgrade 1) LVDS-device with serialized data and for this purpose I have used the SelectIO wizard to set up input buffering, deserializing, etc. It works, but some of the input data appear to be out of phase with the others, meaning an adjustment of the phase for the common clock signal makes some data correct while others are corrupted. The SelectIO wizard enables input delay with the use of the IDELAYE2 primitive, however I am struggling to figure out the resolution of this delay. From what I understand it is not a fixed time delay because of PVT, but I wonder if the delay is significant enought to make a difference for my purpose, up to around 800 ps.

Implementation with IDELAYCTRL checked fails because I am using the SelectIO-instance for 18 individual lines, but do I have to include it at all to use INC/CE to control individual delays or do I have to manually instantiate the primitives without SelectIO to fan out IDELAYCTRL?

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Teacher
Teacher
748 Views
Registered: ‎07-09-2009

what have you set up for you inptu timming constraints.

 

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Contributor
Contributor
740 Views
Registered: ‎08-30-2018

set_multicycle_path  0       -from adc_dco0      -to $clk_dco0;
set_false_path -setup   -rise_from adc_dco0 -fall_to $clk_dco0;
set_false_path -setup   -fall_from adc_dco0 -rise_to $clk_dco0;
set_multicycle_path -1 -hold -from adc_dco0      -to $clk_dco0;
set_false_path -hold    -rise_from adc_dco0 -rise_to $clk_dco0;
set_false_path -hold    -fall_from adc_dco0 -fall_to $clk_dco0;
set_input_delay  -clock adc_dco0             -max            0.25 [get_ports {adc_d_?[*] adc_fco_?[*]}];
set_input_delay  -clock adc_dco0             -min            0.05 [get_ports {adc_d_?[*] adc_fco_?[*]}];
set_input_delay  -clock adc_dco0 -clock_fall -max -add_delay 0.25 [get_ports {adc_d_?[*] adc_fco_?[*]}];
set_input_delay  -clock adc_dco0 -clock_fall -min -add_delay 0.05 [get_ports {adc_d_?[*] adc_fco_?[*]}];
set_output_delay -clock adc_clk_out             -max            2.625 [get_ports {adc_clk_?}];
set_output_delay -clock adc_clk_out             -min            0.5   [get_ports {adc_clk_?}];
set_output_delay -clock adc_clk_out -clock_fall -max -add_delay 2.625 [get_ports {adc_clk_?}];
set_output_delay -clock adc_clk_out -clock_fall -min -add_delay 0.5   [get_ports {adc_clk_?}];
set_false_path   -to                                                  [get_ports {adc_clk_?}]

 adc_d_* are the data lines and adc_dco_ is the 280 MHz clock (DDR).

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Teacher
Teacher
722 Views
Registered: ‎07-09-2009

and you have fixed your pins ?

 

do you pass timming ?

 

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Contributor
Contributor
711 Views
Registered: ‎08-30-2018

Fixed my pins and placed each SelectIO-instance (ISERDESE2/IDELAYE2/IBUFDS) as close as possible to them. Timing fails for intraclock paths [input clk -> IBUFDS -> MMCME2_ADV -> BUFG -> ISERDESE2], but I don't see how that would cause how adjusting the input clock phase makes some data valid in one configuration and other data valid in another. My issue is that all channels do not have an overlapping selection of valid input clock phase, hence the need for IDELAY.

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Contributor
Contributor
703 Views
Registered: ‎08-30-2018

In the wizard IDELAYCTRL is a checkbox. I cannot implement my design with it enabled as there are only 8 of them available, although the documentation says it must be instantiated to use IDELAYE2. However, I can still have delay enabled and access CE/INC without IDELAYCTRL enabled. My question is then is it at all possible to use the wizard for my purpose or will it simply not function without the IDELAYCTRL option?

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Contributor
Contributor
702 Views
Registered: ‎08-30-2018

deleteme.png

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