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Visitor bmoss_lmi
Registered: ‎03-19-2015

Series 7 DDR deserialization

I'm trying to work out how to do a running phase detection for a DDR deserializer in a series 7 part (in this case a Zynq 7030). I've inherited a design originally done on a Spartan-3 with a coregen deserializer that included the phase detection logic. The Series 7 IP in Vivado doesn't provide that deserializer in the design.  


I've read through XAPP585, but the application is different enough that I'm having a difficult time seeing how to adapt it to my circumstances. 


I have a 5 data line inout (4 data and 1 synch channel) from a VITA 1300 camera as well as a DDR clock and the data is not bit striped across the data lanes (where as XAPP585 has a word clock and bit striped data). I'm trying to figure out if there is a way to do the bit deskew without a specific training pattern. We do have a training pattern for the bitslip, but we want the deskew to run on a continuous basis so we can account for any drift. 


I'd appreciate it if anyone can point me towards some information on to contruct bit deskew logic that doesn't rely on an alternating '0' and '1' data pattern. 



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Xilinx Employee
Xilinx Employee
Registered: ‎07-31-2012

Re: Series 7 DDR deserialization



Are you considering the changes due to PVT.  Ideally once trained the data later should not be affected unless your timing is not met fully. 


Probably put a logic to re-train this once you detect a mismatch or anomality in the data.


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Registered: ‎01-04-2013

Re: Series 7 DDR deserialization

I'm using VITA 1300 in my work, but I don't know how to interface with Zynq 7020,can you send some example source code (verilog or vhdl) tome, Thanks a lot.
Best Wishes
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