03-14-2014 11:15 AM
Hello. I am using the Kintex 7 325TFFG900 device. Let me describe my design first, then ask my question.
Using the following banks: 12,13,14,15,16,17,18, I have 3 sets of serial inputs, each set with its own bit clock and frame clock. Each set spans 3 banks: set 1 uses banks 12,13,14. set 2 uses banks 14,15,16. set 3 uses banks 16,17,18.
Each serial input will use a ISERDES. I have placed the bit clock for set 1 on a MRCC input in bank 13, set 2 in bank 15, set 3 in bank 17 (knowing that the MRCC can be routed to adjacent banks). For now, I placed each associated frame clock with its bit clock on the SRCC input. Note that bit clocks and frame clocks are differential.
From the reading I have done, it seems that the SRCC clocks can NOT be routed to adjacent banks and only can be used in its own bank. I need the frame clocks to get to the ISERDES also.
My Question: Can I use the SRCC pin as a normal input (IBUFDS) and specify it as a clock in a CST file, and allow the VIVADO tool infer clock buffers and route to adjacent banks? Or is there another method?
03-14-2014 01:15 PM
The SRCC and MRCC do not directly route to ISERDES, but they do have limitated connections to the clock buffers. The allowed connections are documented in the 7 Series Clocking Resources User Guide UG472 in Table 1-1.
If your interface timing allows for using a BUFG connection instead of a BUFMR->BUFIO connection to be used then you would be OK, if not then you will need to move your frame clock.
03-14-2014 02:22 PM
I read that table. I'm aware that the SRCC and MRCC do not directly route to ISERDES. My MRCC input would use a BUFMR -> BUFIO to get to the ISERDES in all three adjacent banks. And the associated SRCC input would connect to a BUFG -> BUFIO to get to the ISERDES in the same three banks. Other than timing, is this connectivity plausible?
03-14-2014 03:19 PM
The connection should be BUFG only. You would get an routing error if you used the BUFG->BUFIO as this connection is not possible.
03-15-2014 02:13 PM
I think the question is "What is your frame clock for"?
The frame clock in many interfaces is used for determining which bit in the serial stream is the first (or last) bit of the word. If so, then this "frame clock" isn't actually a clock, but is merely a data signal to be captured by another ISERDES.
Assuming your interface is synchronously clocked, then
- the MRCC pin goes to a BUFMR (as you said)
- the BUFMR goes to all three BUFIO and BUFR in the three adjacent banks
- you MUST go through the procedure to synchronize the three BUFR dividers with eachother - this is described in the section "BUFR alignment" in Appendix A of UG472
- the BUFIOs drive the CLK pins of all the ISERDES - including the ISERDES that is driven by the frame clock
- the BUFRs drive the CLKDIV pins of all the ISERDES (also including the frame clock)
Now you need a little state machine to look at the output of the ISERDES that is capturing the frame clock - you need to pulse BITSLIP once every couple of clocks until rising edge of the frame clock is aligned to be in the Q0 (or Qn) output bit of the ISERDES. Since the "frame clock" is now in the right place, the entire interface will be framed (again, assuming the interface is synchronous and clocked synchronously).
03-17-2014 08:46 AM
The frame clock is the bit clock divided by 7, in my case, which defines the bit stream word boundry. This is typically what a BUFR would do, and would connect to the CLKDIV input of the ISERDES.
And, yes I plan to create a state machine to get to the correct word framing of the ISERDES output.
I just wanted to verify that the frame clock(currently located on a SRCC input, of bank 13 for example) was able to get to the ISERDESs on adjacent banks, 12 and 14. The interface is synchronous and clocked as such.
03-17-2014 09:31 AM
Please re-read avrum's post #15. The frame input should not be used to clock the ISERDES it should be used only as an alignment bit.
03-17-2014 01:53 PM
I think you are missing my point. (reference the UG471, 7 series FPGAs SelectIO Resources User Guide) I am using the ISERDESE2, Master/Slave, 14 bit width expansion, serial to parallel, DDR, NETWORKING mode. My bit clock is the DDR CLK input to the block. My frame clock is intended to be CLKDIV input to the block. The timing relationship of these two clocks looks to be what is intended for this ISERDESE2 configuration. Now I may use the bitslip for bit/word alignment if needed. My word width is 14 bits, the max capability of the ISERDESE2.
So again, I know that the bit clock, on a MRCC input, can reach all ISERDESE2s in adjacent banks.
And again, is it possible for the frame clock on a SRCC input, located next to the bit clock MRCC, to reach all the same ISERDESE2s? I have read the UG472 7 series FPGAs Clocking Resources User Guide, and not sure about the routing of the SRCC pin. Thank you.
03-17-2014 02:08 PM
The Single Region Clock Capable (SRCC) pin can not clock a I/O SERDES in adjacent regions. Only the Multi Region Clock Capable (MRCC) can do so via the BUFMR. SRCC could connect via local route, but it's not likely to impossible that that will work out in terms of timing. So move your Byte/Frame clock to a MRCC. Or, I don't know how fast your source synchronous interface has to run, but a BUFG may be able to drive your I/O Serdes since it has access everywhere. Use a MMCM if needed for phase shifting (clock alignment).