03-12-2018 03:30 AM
I'm trying to change the default program for a Xilinx Spartan 6 fpga to automatically forward data from rx port to tx port.
The fpga is part of an USRP B200 module.
Some errors are returned when i want to run the program because some signals are calling the same port.
Is it possible to change something in the Verilog source code to implement this purpose?
03-12-2018 04:25 AM
Can you post the original code and the changes you've made?
Are you aiming to maintain the original TX functionality and also have the RX data passed through to the TX, or do you want to just do the passthrough? The latter is easy, the former is tricky.
03-12-2018 06:02 AM