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Newbie
Newbie
13,478 Views
Registered: ‎08-07-2013

Setting PULLUP/PULLDOWN on a differential pair in Vivado

Hi,

 

I'm sorry if this has been answered before, but I couldn't find anything in the forums. I am working with the Zedboard on Vivado and are trying to set a PULLUP constraint on a differential inout pair.

 

If I set a pullup on the _P port ( set_property PULLUP true [get_ports PinX_P] ) in the *.xdc constraints file, both the _P and the _N ports are being pulled up, which does not seem smart on a diffenential pair :)

 

If I set a pulldown on the _N port ( set_property PULLDOWN true [get_ports PinX_N] ) both the _P and the _N ports are being pulled down...

 

If I set both of the constraints at the same time, both ports are being pulled to whichever direction got set last, so in the order above both are being pulled down; if I first write the pulldown line for the _N port and then the pullup line for the _P, both lines are being pulled up.

 

Additionally I tried changing pullup/pulldown behaviour in the "I/O Planning"-view for the two pins after synthesis (see UG935), but the outcome is the same. If I change one pin, the other gets set to the same value. Also, the tcl command that get executed looks almost identical: set_property PULLUP {1} [get_ports PinX_P]

 

I just want to know if this behaviour is expected and/or known to be a problem. A workaround would also be appreciated.

Currently I have adapted my design to work with KEEPER on both ports, since the behaviour there seems to be correct (one port being pulled up while the other is being pulled down)

 

Thanks in advance for any help.

 

 

TLDR: How do I set the non-driven state of a differential pair to be pullup on one port and pulldown on the other in Vivado?

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8 Replies
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Xilinx Employee
Xilinx Employee
13,476 Views
Registered: ‎09-20-2012

Hi,

 

Check this article http://www.xilinx.com/support/answers/53368.htm .It describes the same problem but it talks about PlanAhead. 

 

Thanks,

Deepika.

Thanks,
Deepika.
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Highlighted
Newbie
Newbie
13,467 Views
Registered: ‎08-07-2013

Thanks a lot for the quick reply!

 

Your answer seems like a reasonable workaround for the time being (until this issue gets addressed), but unfortunately I do not know how to do this in Vivado. Can I still access the FPGA Editor somehow? Is there a new tool which includes this functionality?

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Xilinx Employee
Xilinx Employee
13,439 Views
Registered: ‎09-20-2012

Hi,

 

I was trying to find out a way to do the same in Vivado. I will post here if I learn some thing on this.

 

Another workaround which you can use for now is to instantiate PULLUP and PULLDOWN in the HDL.

 

Thanks,

Deepika.

Thanks,
Deepika.
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Xilinx Employee
Xilinx Employee
13,364 Views
Registered: ‎09-20-2012

Hi Edwin,

 

Thanks for bringing this issue in to our notice.

 

Our developers are currently looking in to this for a fix. There is an internal Change Request 687009 on this. This may be supported in a future release of vivado.

 

Cheers,

Deepika. 

Thanks,
Deepika.
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Observer
Observer
9,298 Views
Registered: ‎11-14-2013

Hi buddy,

 

I found this issue is not fixed in vivado 2015.2.

 

AR#53368 says:

"If the desire is to have opposite pull-types, the solution is to instantiate the PULLUP and PULLDOWN primitives in the design RTL, instead of using the PULLUP and PULLDOWN attributes. "

 

Vivado gave a warning about pullup/pulldown primitives and ignore thant.

Can anybody give me a hint?

 

Thanks,

 

Kim

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Scholar
Scholar
9,267 Views
Registered: ‎06-05-2013

@kimwen There has been change in the tool starting from 2014.1. Please start a new thread by pointing this to old thread to get quick attentation.

 

Meanwhile i will try this

-Pratham

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Observer
Observer
9,254 Views
Registered: ‎11-14-2013

Hi Pratham,

 

The RTL code is very simple.

 

module blvds_test(
input dp,
input dn,
output rx
    );
 
 
  IBUFDS #(
      .DIFF_TERM("FALSE"),       // Differential Termination
      .IBUF_LOW_PWR("TRUE"),     // Low power="TRUE", Highest performance="FALSE"
      .IOSTANDARD("LVDS_25")     // Specify the input I/O standard
   ) IBUFDS_inst (
      .O(rx),  // Buffer output
      .I(dp),  // Diff_p buffer input (connect directly to top-level port)
      .IB(dn) // Diff_n buffer input (connect directly to top-level port)
   );
 
    
     PULLUP PULLUP_inst (
      .O(dp)     // Pullup output (connect directly to top-level port)
   );
    
     PULLDOWN PULLDN_inst (
      .O(dn)     // Pulldown output (connect directly to top-level port)
   );
endmodule

 

 

 

Get following warning message :

[Constraints 18-4379] The N and P sides of the following differential port(s) have connections to PULLUP/DOWN primitives that conflict with the setting of iconstr.diffPairPulltype param.  The PULLUP/DOWN connection for these ports will be ignored. dn, dp

 

I checked the IO properties,PULLUP on both dp and dn.

 

Kim

 

 

 

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Scholar
Scholar
9,248 Views
Registered: ‎06-05-2013

@kimwen Please check your inbox

-Pratham

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