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Visitor
Visitor
2,149 Views
Registered: ‎01-29-2018

Setting up LVDS_25 on Arty S7

I am trying to send a clock signal out of my Arty S7 board over LVDS. I have done the following steps to try to get LVDS output:

 

  1. Create Block Design under IP Integrator
  2. Select Utility Buffer
  3. Change the Utility Buffer type to OBUFDS
  4. Connect input and output ports to the buffer
  5. Generate Block design
  6. In my top level Verilog file I instantiate the generated IP. The clock in signal is connected to an input I have named Clock100M. This is the onboard clock.
  7. Synthesize design
  8. Open elaborated design
  9. Open I/O Ports view under Window
  10. I set the I/O standard for Clock100M to be LVCMOS25 (it’s single ended)
  11. I set the I/O standard for my output pins to LVDS_25
  12. I run implementation, bitstream generation, and I program the device

After all this, I still get 0V output. Are there any steps that I am missing? I have checked that the pin can send out single-ended data without issue.

 

Thanks

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Moderator
Moderator
2,129 Views
Registered: ‎04-18-2011

Hi
Are you setting a location constraint for the IO that matches the board? Are you getting any critical warnings during synthesis or implementation?
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Visitor
Visitor
2,125 Views
Registered: ‎01-29-2018

Yes I am setting location constraints for all the pins. I have not seen any critical warnings during synthesis or implementation.

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Moderator
Moderator
2,093 Views
Registered: ‎04-18-2011

So you are sure the input clock is running? Try make a counter amd check with an ILA that it is clocking the counter. What is connected to this output IO? Could it be getting pulled down somehow?
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Visitor
Visitor
2,086 Views
Registered: ‎01-29-2018

Yes I am sure the clock is running. I changed the I/O standard from LVDS to LVCMOS and I was able to measure the single ended clock at the output. As far as what is connected to it: I currently have a 100 ohm termination resistor across the P and the N pins and have set "Off-Chip termination" to FD_100 in the I/O Ports tab.

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Moderator
Moderator
2,081 Views
Registered: ‎04-18-2011

I'd try it outside of IPI then If I was you just to make sure the utility buffer is not the cause of it. 

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Visitor
Visitor
2,079 Views
Registered: ‎01-29-2018

As far as I know the OBUFDS utility buffer from the IP integrator is the way to create differential output. Could you please explain how to setup LVDS output without using the IP integrator?

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Visitor
Visitor
1,990 Views
Registered: ‎01-29-2018

Bump

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Moderator
Moderator
1,961 Views
Registered: ‎04-18-2011

I was suggesting a test where you didn't use IPI and just wrote some simple verilog to do pass out a clock on this IO pair. This would rule out a problem with the ipi. I would try some sort of very slow signal so we know this is not a signalling problem in hardware
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Moderator
Moderator
1,913 Views
Registered: ‎07-23-2015

@kevin.wenger The Banks are powered off 3.3V on the S7 board and hence LVDS_25 is not a valid output setting. 

- Giri
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