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394 Views
Registered: ‎02-12-2019

Signal initialization in Virtex II (XC2VP50) with ISE 10.1i

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I have seen recent posts verifying that in modern tools and devices the following VHDL signal instantiation will have an initial value after configuration of '1', but does this hold true for older devices and tools?

Specifically the VirtexII Pro (XC2VP50) and ISE 10.1i ?

signal enable : std_logic := '1';

Will my signal "enable" have the value of '1' after configuration without any reset block?

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Xilinx Employee
Xilinx Employee
355 Views
Registered: ‎08-25-2010

回复: Signal initialization in Virtex II (XC2VP50) with ISE 10.1i

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Hi dwalto08@harris.com

 

Yes, the initial state after configuration is 1 for signal enable.

Thanks
Simon
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2 Replies
Xilinx Employee
Xilinx Employee
356 Views
Registered: ‎08-25-2010

回复: Signal initialization in Virtex II (XC2VP50) with ISE 10.1i

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Hi dwalto08@harris.com

 

Yes, the initial state after configuration is 1 for signal enable.

Thanks
Simon
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Don't forget to reply, kudo, and accept as solution.
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343 Views
Registered: ‎02-12-2019

回复: Signal initialization in Virtex II (XC2VP50) with ISE 10.1i

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Thank you Simon. I could find no documentation of that in the datasheet, appnotes, or white papers that specifically addressed Virtex II.
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