I am simulating the input of differential ADC data (8 input pairs) coming into the FPGA using the SERDES. At the moment I am just using an 100 MHz test clock with inputs tied high, but hope to scale this up to a bitclock rate of 450 MHz.
Here are my wave-forms so far with the 100 MHz. Looks like the data outputs for a couple clock cycles then XXX's afterwards (not sure why this is). I appreciate the help. I believe this may be related to the reset behavior but not quite sure what.