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Registered: ‎07-02-2020

Simulation of SelectIO LVDS SERDES of Zynq FPGA

I am simulating the input of differential ADC data (8 input pairs) coming into the FPGA using the SERDES. At the moment I am just using an 100 MHz test clock with inputs tied high, but hope to scale this up to a bitclock rate of 450 MHz.

Here are my wave-forms so far with the 100 MHz. Looks like the data outputs for a couple clock cycles then XXX's afterwards (not sure why this is). I appreciate the help. I believe this may be related to the reset behavior but not quite sure what.

Screenshot from 2021-07-20 18-18-31.png

Screenshot from 2021-07-20 18-25-15.pngScreenshot from 2021-07-20 18-25-23.pngScreenshot from 2021-07-20 18-25-32.png

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