01-21-2021 11:33 AM
I have an FPGA clocking relatoed problem that i would like to discuss with you.
My target device is a 7 series Zynq 7000.
I have a slow clock signal (1 Mhz or so) that I need to multiply let's say by 4.
The MMCM is accepting a minimum frequency of 10 Mhz, so it wont work directly.
I can work, let's say at 100 Mhz and crete a clock enable strobe, but that would imply that my clock will have jitter of the 100Mhz clock period.
Would it work if i sample the slow clock with 100 Mhz, create the mutiplied clock with a counter and then input this signal to a PLL?
Would it clean it of the jitter?
(i'm attaching an image to clarify)
01-27-2021 01:34 AM
I've not had the need to create a clock at this frequency so I will leave it to the Community to suggest techniques that have worked.
I did want to mention that the timing would need to be handled carefully so you are not timing the 100MHz.
The UFDM has good sections on Clock Enables and how to constraint them.
01-27-2021 04:08 AM
Hello Sandy, thanks for the reply!
I don't understand completely what you are trying to tell me...
The 100Mhz Clock domain will be constrained by just telling the 100M frequency in the .xdc.
That would be a bit of an overconstraint because there will be paths that can be relaxed by setting multicyles, but I can safely afford this waste in my design.
Let's say that this slow clock is not driving any register in the FPGA, all that has to happen is a multiplication.