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Some questions about 7 series CLB

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Hi, as a beginner in the Xilinx FPGA, I have several questions about internal of CLB structure of 7 series. 

 

The first question is about the SLICEL and SLICEM.

 

 

As shown in the below figure of SLICEM, it contains four special blocks that can be used as FF, LUT, or RAM, how can I call this block? Is it a just LUT? I am confusing because both slices have four 6 input LUT (located on the leftmost side of the two figures) with different shape and different input signals. 

 

SLICEM.JPG

SLICEM Figure

 

 

 

 

 

SLICEL.JPG

SLICEL Figure

 

The second question is about the RAM. The document said the SLICEM can only be used as a RAM component.

 

I am wondering why SLICEL cannot be used a RAM even though it has 4 FF/LAT components and 4 FF components. 

Is it because each FF can only store 1bit data, but the LUT in SLICEM can store 6bits of data? 

 

If it is correct, which signal allows the LUT in SLICEM to be used as a RAM?

And Is it available by adding the re-writable capability to the LUT which is originally the read-only memory?

If it is not correct, what is the purpose of the signal W[6:1], DI2, and DI1?

 

And the last questions is about the port definition of the RAM.

quad port.JPG

Above figure shows the definition of the 32 X 2 Quad port RAM, but I couldn't understand why it is 32X2 Quad port.

 

If my understanding is correct, the first D RAM has one port for read and write, and

other ports (C, B, and A) have dedicated read lines, which means Quad port. 

However, why it is 32 X 2 Quad port?

What parts of the above figure make it "32 X 2" Quad port RAM? 

 

Could anyone correct my guess or please explain more about the CLB? 

 

 

 

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Explorer
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Registered: ‎03-31-2016

@jaehyuk wrote:

 

 

As shown in the below figure of SLICEM, it contains four special blocks that can be used as FF, LUT, or RAM, how can I call this block? Is it a just LUT? I am confusing because both slices have four 6 input LUT (located on the leftmost side of the two figures) with different shape and different input signals. 

 


No, it does not contain any single block that can be used as FF or LUT or RAM, the FF block is totally separate from the LUT block and they are not interchangable.  A CLB is basically constructed of two blocks types, the logic element type or LUT (which can also be used as RAM in SLICEMs) and the storage element type which can be used as a FF or Latch.  Current CLBs use 4 of each of these types.

 

All slices contain FF but FF are not RAM because they cannot be addressed by themselves  A value can be stored but you have no address so it isn't memory by definition. You could use another level of logic to select between the output of several FFs to build a RAM though.

 

All slices also contain LUTs and LUTs are basically RAM because some number of bits go in, which you can think of as an address, and a single bit comes out.  If the content of this LUT can be changed dynamically this can be used as RAM in the user design.

 

In a SLICEL the content of the LUTs are only set by the configuration but in a SLICEM the content can be dynamically updated.  That is why the SLICEM by itself can be called a RAM but the SLICEL cannot.


@jaehyuk wrote:

Above figure shows the definition of the 32 X 2 Quad port RAM, but I couldn't understand why it is 32X2 Quad port. 


The "32" part comes from the address width of 5 which means it can select from 32 addresses/elements.

The "X2" part comes from the fact that there are 2bits of output DOx[0] and DOx[1].

 

The "Quad port" part comes from there being 4 different address connection.

 

 

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Scholar
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Registered: ‎02-27-2008

In teaching my class,

 

I use a textbook I co-authored with Jesse Jenkins, and the late Peter Alfke:  "Virtex Under the Hood, 2nd Edition."  I revised it completely last year, so it is up to date.  I have no copyrights, or financial interest in the book -- it is there to be used to instruct and educate.  Attribution is encouraged if shared.

 

If you wish a copy, email me at:

 

austin@xilinx.com

 

I use the US patent office to get details of how Xilinx designs their CLB, as it is all public, and explained such that anyone 'skilled in the art' may understand how it is done.

 

The LUT is 64 6T memory cells.  The LUTRAM/SRL slice allows their use as 64 addressable bits (LUTRAM), or as 32 shift register bits (SRL re-arranges them into a master-slave FF chain).  The non-LUTRAM/SRL slice does not have the connections/devices for the 64 bit LUT to be used as LUTRAM, nor SRL.

 

The 8 DFF are programmable as shown.

 

 

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
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Registered: ‎03-31-2016

@jaehyuk wrote:

 

 

As shown in the below figure of SLICEM, it contains four special blocks that can be used as FF, LUT, or RAM, how can I call this block? Is it a just LUT? I am confusing because both slices have four 6 input LUT (located on the leftmost side of the two figures) with different shape and different input signals. 

 


No, it does not contain any single block that can be used as FF or LUT or RAM, the FF block is totally separate from the LUT block and they are not interchangable.  A CLB is basically constructed of two blocks types, the logic element type or LUT (which can also be used as RAM in SLICEMs) and the storage element type which can be used as a FF or Latch.  Current CLBs use 4 of each of these types.

 

All slices contain FF but FF are not RAM because they cannot be addressed by themselves  A value can be stored but you have no address so it isn't memory by definition. You could use another level of logic to select between the output of several FFs to build a RAM though.

 

All slices also contain LUTs and LUTs are basically RAM because some number of bits go in, which you can think of as an address, and a single bit comes out.  If the content of this LUT can be changed dynamically this can be used as RAM in the user design.

 

In a SLICEL the content of the LUTs are only set by the configuration but in a SLICEM the content can be dynamically updated.  That is why the SLICEM by itself can be called a RAM but the SLICEL cannot.


@jaehyuk wrote:

Above figure shows the definition of the 32 X 2 Quad port RAM, but I couldn't understand why it is 32X2 Quad port. 


The "32" part comes from the address width of 5 which means it can select from 32 addresses/elements.

The "X2" part comes from the fact that there are 2bits of output DOx[0] and DOx[1].

 

The "Quad port" part comes from there being 4 different address connection.

 

 

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@necare81 Thanks for a great answer. I have one further question about the LUTs in SLICEM. If my understanding is correct, one LUT in the SLICEM can address up to 32 elements (through 5 bits of input) and for each address, the LUT can store two values. Therefore 32 * 2 = 64 bits of data can be stored in one LUT. Is it correct? I appreciate your help again.

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@austin Thanks for a great answer and further help. I was having a hard time to understand CLB and other related topics of Xilinx FPGA, as a newbie in this field. I hope that I could get a copy of your book :D. I appreciate your help once again. Regards, Jaehyuk.

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Scholar
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On its way,

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
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