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Explorer
Explorer
478 Views
Registered: ‎05-25-2016

Source synchronous serial stream - best approach

Hello, 

 

I have a source synchronous serial stream coming in to a Kintex 160 FPGA.  I actually have 16x of these serial streams and they are all LVDS coming from a chip (THS788) at up to 300Mhz speeds.  Is it possible to use SERDES in the IOB to receive this data.  The serial stream could be up to 40 bits long and as I read the select IO resource documentation they are limited.  I have then read on the forums that you can cascade SERDES blocks together, but I'm unsure if I can cascade enough to receive a 40 bit stream.  Would it be better to plan on using 1 SERDES primitive or 2 cascaded together to receive the data in multiple "chunks"? 

 

I'm looking for general guidance and a best approach to implement these interfaces.  Below is a picture of an example serial stream the THS788 would be sending to the FPGA.

 

41.jpg

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Xilinx Employee
Xilinx Employee
420 Views
Registered: ‎06-30-2010

Re: Source synchronous serial stream - best approach

To clarify you are doing a 1:40 interface, the serial clock rate is 300Mhz and so the parallel rate is 7.5Mhz is that correct?

You can cascade but only 2 SERDES can be used so that 14 bits, see page 155 for more detail: http://www.xilinx.com/support/documentation/user_guides/ug471_7Series_SelectIO.pdf

you can do as you suggest and capture the serial data at either 8 bits or 14 and then combine to 40 bits in the fabric.
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