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Observer
Observer
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Registered: ‎06-07-2012

Spartan 6 Block Memory Reset

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I am using the block ram in a Spartan 6 FPGA.

I used the IP Core Generator to create the Verilog model.

Ram block used as Simple Dual Port.

I want to be able to clear the ram's content but I don't see a PortA Reset selection using the IP Core Generator even though it is discussed in many Xilinx documents and it is part of the Verilog model generated.

Can a Simple Dual Port implementation of a Ram Block be reset/cleared?

 

Thanks

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Xilinx Employee
Xilinx Employee
227 Views
Registered: ‎08-13-2007

Re: Spartan 6 Block Memory Reset

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The reset doesn't clear the RAM array itself - it only clears the respective output registers.

You'll likely need to write back over the contents explictly.

For more info: https://www.xilinx.com/support/documentation/user_guides/ug383.pdf

 

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Xilinx Employee
Xilinx Employee
228 Views
Registered: ‎08-13-2007

Re: Spartan 6 Block Memory Reset

Jump to solution

The reset doesn't clear the RAM array itself - it only clears the respective output registers.

You'll likely need to write back over the contents explictly.

For more info: https://www.xilinx.com/support/documentation/user_guides/ug383.pdf

 

View solution in original post

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Observer
Observer
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Registered: ‎06-07-2012

Re: Spartan 6 Block Memory Reset

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Thanks

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