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noisilysilent
Observer
Observer
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Registered: ‎05-24-2017

Spartan 6 : Clock Generator => DCM => PLL for HDMI 720p output

Hi all,

I'm having a hard time setting up my design.
Platform : Spartan 6 - Digilent Atlys.
SDK : ISE 14.7, XPS Project

I've been trying to modify Digilent HDMI Demo project in ISE 14.7.

Original design by Digilent was :
Reference clock 100MHz => Clock Generator (CLKOUT2) 75MHz => PLL Module (CLKOUT 1 75MHz, CLKOUT2 150MHz)

This design produces ont its HDMI output some signal that most TV will accept but some other HDMI devices will not accept it as it should be 74.25MHz and not 75MHz.

So I've been trying to create my own core to generate a 74.25MHz clock between Clock Generator and PLL Module.

Hence new design is :
Reference clock 100MHz => Clock Generator (CLKOUT3) 100MHz => custom DCM core 74.25MHz => PLL Module (CLKOUT 1 74.25MHz, CLKOUT2 148.50MHz)

There are a few problems that I am facing.

1/ I am a total noob and don't master xilinx tools at all, nor basic FPGA architecure. So my custom DCM module was built from scratch with a text editor. It only consist of a VHDL file and a MPD file (attached to this message), there might be things missing such as constraints...
First problem is I cannot connect DCM LOCK (O) port to PLL RST (I) port in XPS, it does not appear in the scrolling menu of eligible ports for PLL RST. Any Hint ?

2/ I changed PLL module COMPENSATION parameter from INTERNAL to DCM2PLL due to an error in bitstream generation saying that PLL compesation parameter should be set to DCM2PLL. I then tried to export and got the following error :

********************************************************************************
ERROR: 1 constraint not met.

PAR could not meet all timing constraints. A bitstream will not be generated.

To disable the PAR timing check:

1> Disable the "Treat timing closure failure as error" option from the Project Options dialog in XPS.

OR

2> Type following at the XPS prompt:
XPS2ff6000set enable_par_timing_error 0
********************************************************************************

So I disabled "Treat timing closure failure as error" and finaly succeed in generating bitstream.

However, things don't work : there is no output signal on the HDMI output and I don't have a single hint about where I should start to debug this problem

Any idea of what could be wrong ?
Many thanx to those who will help

Cheers

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3 Replies
noisilysilent
Observer
Observer
237 Views
Registered: ‎05-24-2017

No one to help me with this issue ?

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mwerner2000
Adventurer
Adventurer
197 Views
Registered: ‎06-05-2015

Dear noisilysilent,

well the reason why your design doen't work is that first of all you do need a very accurate and stable 74.25 MHz clock. It is usually a good idea to use special oscillators that provide this frequency. Using a PLL/DCM for the purpose of Video clocking is not a good idea, since the PLL will introduce jitter and seldomly achieve the exact frequency needed. Also cascading PLLs is a very bad idea. Try to use only one PLL/DCM and make sure that the resulting frequency can be achieved (if its 74.26 then it won't work reliably).

Secondly, the synthesis tool does tell you that it cannot meet timing. This means either your constraints are incorrect, your design is not fast enough or there is some issue with clock domain crossing, which need a false path constraint. Never IGNORE these kinds of errors, since they mean there is something seriously wrong with your design. If the synthesis tool does not want to generate a bitstream, then you shouldn't bypass these errors/warnings. There are very few exceptions, but in general it is a good idea to fix the problem and not bypass the warning.

 

Best regards,

Martin

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mwerner2000
Adventurer
Adventurer
184 Views
Registered: ‎06-05-2015

I just had a quick look at the Atlys board schematic. Well there would be the option to use the clock of an incoming HDMI stream (Pin H17 / H18 on the FPGA) to get a good clock for sending data. I assume this only works if there is a RX HDMI connection. But for testing this could work. You don't need to do anything with the RX HDMI data. Only use an IBUFDS+BUFG to get the clock and use it directly as your main system clock.

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