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Visitor nav117
Visitor
1,184 Views
Registered: ‎10-11-2018

Spartan 6 FPGA as LVDS receiver

        My project takes video input in Two Port Open LDI format. I use Spartan 6 FPGA as LVDS receiver.

 

        The following pin assignment is made:

Port_Assig.PNG 

               

 

        You can clearly see that the clock lanes of both Port 0 and Port 1 are located in RB region of Bank 1 whereas few lanes of Port 0 is in RT Region.

 

        Due to this I am getting some contours at the output video.

 

        So I mapped the Port0_CLK signal to F17 and F18 pin which belong to RT region and use two separate PLL’s to generate the sampling clocks for RT and RB region. And similarly two separate BUFPLL’s to generate Serdes strobe signals.

 

        But get the below error:

 

ConstraintResolved NO placeable site for

clk_inst/rx_bufpll_inst_Bank1

ERROR:Place:1172 - The BUFLL/BUFPLL_MCB instance <clk_inst/rx_bufpll_inst_Bank1>

needs to have all of its IOB loads placed into its same IO bank. However, due

to user-specified constraints, the BUFLL/BUFPLL_MCB instance

<clk_inst/rx_bufpll_inst_Bank1> and its IOB load <in_lvds0<0>> cannot be

placed in the same IO bank. These constraints could be LOCATION or AREA

constraints on <clk_inst/rx_bufpll_inst_Bank1>, or <in_lvds0<0>>, or other

components connected to them, which could impose an implicit constraint on

them. Please check user-specified constraints on all of these components to

ensure their combination is not infeasible.

 

Could you please help me to resolve this error?

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10 Replies
Xilinx Employee
Xilinx Employee
1,159 Views
Registered: ‎06-30-2010

Re: Spartan 6 FPGA as LVDS receiver

what is the exact part / package that you are using ?

the problem is this port <in_lvds0<0>> what pin is that constrained to?
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Visitor nav117
Visitor
1,125 Views
Registered: ‎10-11-2018

Re: Spartan 6 FPGA as LVDS receiver

Thanks for your Response

 

Part Number : XC6SLX9-2CSG324C

 

These are the only constraints specified regarding the nets in_lvds0_Clk and in_lvds0

NET "in_lvds0_clk" LOC = F17 |IOSTANDARD = LVDS_33;
NET "in_lvds0_clk_N" LOC = F18 |IOSTANDARD = LVDS_33;
NET "in_lvds0[0]" LOC = C17 |IOSTANDARD = LVDS_33;
NET "in_lvds0_N[0]" LOC = C18 |IOSTANDARD = LVDS_33;

 

Inorder to avoid the skew we have mapped both the clk and data line in the same bank.

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Xilinx Employee
Xilinx Employee
1,117 Views
Registered: ‎06-30-2010

Re: Spartan 6 FPGA as LVDS receiver

here is the link to the ascii pinout file for that package for completeness: https://www.xilinx.com/support/packagefiles/s6packages/6slx9csg324pkg.txt

So these are the pins you have used:

F17 1 RT IO_L35P_A11_M1A7_1
F18 1 RT IO_L35N_A10_M1A2_1
C17 1 RT IO_L29P_A23_M1A13_1
C18 1 RT IO_L29N_A22_M1A14_1

So they are all in Bank 1 and their BUFIO2 is the right Top so that looks ok.

in situations like this i would try leaving the data un-loced and see where it gets placed that can sometimes indicate what the problem is.
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Visitor nav117
Visitor
1,112 Views
Registered: ‎10-11-2018

Re: Spartan 6 FPGA as LVDS receiver

in_lvds0_N[0]_notAssigned.PNG

When the in_lvds0[0] is Un-loced, There is no assignment for the pin post synthesis.

 

onlyOutputView.PNG

And can you help us in viewing the Input Pins numbers in "View and Edit Routed design"

in_lvds0_N[0]_notAssigned.PNG
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Visitor nav117
Visitor
1,050 Views
Registered: ‎10-11-2018

Re: Spartan 6 FPGA as LVDS receiver

When leaving it un-loced, lines get mapped in Bank 3

But hardware layout is done for Bank 1 region only.

Can we somehow forcibly match to already hardwired Bank1 ports itself through compromising on some functions.

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Xilinx Employee
Xilinx Employee
1,044 Views
Registered: ‎06-30-2010

Re: Spartan 6 FPGA as LVDS receiver

we are just trying to see what connectivity the placer will use if it is not loc'ed. can you fully implement the design and let us know where the pins get placed, we can then try and compare the site types to see what the issue could be
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Visitor nav117
Visitor
1,036 Views
Registered: ‎10-11-2018

Re: Spartan 6 FPGA as LVDS receiver

Upon completion of full design, the pin gets mapped in Bank 3 region only

What we want to forcibly match it to bank 1 because of hardware layout restriction.(That is to keep the differential data line and its clock in the same bank region)

 

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Xilinx Employee
Xilinx Employee
1,027 Views
Registered: ‎06-30-2010

Re: Spartan 6 FPGA as LVDS receiver

I understand that what pins in Bank 3 get used?

 

The next step would be to move these to the same position in bank 1 to see if they map there as well and then we should be able to understand why the current pinout is causing problems. 

 

 

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Visitor nav117
Visitor
962 Views
Registered: ‎10-11-2018

Re: Spartan 6 FPGA as LVDS receiver

When we map the pins to Bank3 region, there is no error encountered. Error occurs only when we map to Bank1

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Visitor nav117
Visitor
893 Views
Registered: ‎10-11-2018

Re: Spartan 6 FPGA as LVDS receiver

We use 2 port open LDI protocol

The pin assignments are done as shown below

Lvds Port 1

Clk

Data line 1

Data line 2

Data line 3

Data line 4

Region

RB (Bank 1)

RB (Bank 1)

RB (Bank 1)

RB (Bank 1)

RB (Bank 1)

      

Lvds Port 2

Clk

Data line 1

Data line 2

Data line 3

Data line 4

Region

RB (Bank 1)

RB (Bank 1)

RT (Bank 1)

RT (Bank 1)

RT (Bank 1)

 

Plotting Lvds port 1 signals alone, we find the output to be perfect but when we include port 2 signals we find such green line distortions in output.

green.png

We felt the issue is because the clock and data lines of port 2 are in different regions, thus we mapped the clock lines alone to RT Region of Bank1.

Lvds Port 1

Clk

Data line 1

Data line 2

Data line 3

Data line 4

Region

RB (Bank 1)

RB (Bank 1)

RB (Bank 1)

RB (Bank 1)

RB (Bank 1)

 

Lvds Port 2

Clk

Data line 1

Data line 2

Data line 3

Data line 4

Region

RT (Bank 1)

RB (Bank 1)

RT (Bank 1)

RT (Bank 1)

RT (Bank 1)

 

Doing so we Get the below error

ERROR: Place – Constraint Resolved NO placeable site for clk_inst/rx_bufpll_inst

But if we change it to Bank 3 then we find No errors

Lvds Port 1

Clk

Data line 1

Data line 2

Data line 3

Data line 4

Region

LT (Bank 3)

LT (Bank 3)

LT (Bank 3)

LT (Bank 3)

LT (Bank 3)

 

Lvds Port 2

Clk

Data line 1

Data line 2

Data line 3

Data line 4

Region

LB (Bank 3)

LT (Bank 3)

LB (Bank 1)

LB (Bank 1)

LB (Bank 1)

 

Is there any restrictions with bank 1?

Please do help us

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