10-14-2019 06:46 AM
Hi to all,
I am working with Spartan-6 IDELAY to deserialize a 200MHz DDR input stream (400Mbps).
Based on the Spartan-6 data sheet (DS162) Table 39, I calculated the maximum number of taps for 400Mpbs (2.5ns period) as 62 taps. I am using the equation stated in the note. 2 of the table based on the speed grade -3. However, when I am playing with the IDELAYs by incrementing/decrementing the taps, I have found the number of taps is around 104.
Am I right in taps number calculation? If yes, then why the real number of taps is different?
10-14-2019 07:58 AM