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Visitor
Visitor
1,114 Views
Registered: ‎11-10-2018

Spartan6 3.3V input on a Bank3 with 2.5V VCC_IO

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I'm wondering weather connecting a 3.3V input to a Pin in a bank that is powered with 2.5V cause damage? 

I have a Enclustra MX2 Spartan6 XC6SLX45T board where I can select the VCC_IO voltage for Bank0,2,3 between 3.3V and 2.5V.
When running against a Cypress FX3 this VCC_IO is set to 2.5V.
However I want to monitor (input only) some GPIO's that are 3.3V, i.e. IO_L46N_M3CLKN_3 (G1) of Bank3.

Would it cause damage? Do the input level have to match VCC_IO? 

 

 

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Xilinx Employee
Xilinx Employee
1,033 Views
Registered: ‎06-06-2018

Hi @eiselekd ,

Yes, you can interface with diffrent VCCO. 

For Example, [1] If you are using LVCMOS Standard then, you need to ensure that VOH and VOL of transmitter are below the VIH and VIL of the reciver., for succesfull interfacing.

                       [2] If you are using LVDS Standard then, you can refer this AR#43989 , Since LVDS is not rail to rail voltage. If you satisfy the conditions mentioned in that you can interface with diffrent                               VCCO.

 

Hope you got the concept of interfacing, with different VCCO.

 

Regards,

Deepak D N

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Please reply or give kudo or Accept As a Solution.

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Regards,
Deepak D N
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Please Kudo and Accept as a Solution, If it helps.
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Professor
Professor
1,087 Views
Registered: ‎08-14-2007

For inputs, you can have 3.3V LVCMOS in a 2.5V powered bank.  See table 1-5 on page 39 of UG381.

-- Gabor
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Advisor
Advisor
1,057 Views
Registered: ‎04-26-2015

@eiselekd In addition to what has been said above, if you look up DS162 (Spartan 6 datasheet) you'll find that the maximum recommended input voltage is 4V (commercial temperature range) or 3.95V (industrial/extended temperature range) - it has no dependence on either the I/O standard or any of the supply voltages. As a result, there should be no risk to just connecting the 3.3V signal directly.

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Xilinx Employee
Xilinx Employee
1,034 Views
Registered: ‎06-06-2018

Hi @eiselekd ,

Yes, you can interface with diffrent VCCO. 

For Example, [1] If you are using LVCMOS Standard then, you need to ensure that VOH and VOL of transmitter are below the VIH and VIL of the reciver., for succesfull interfacing.

                       [2] If you are using LVDS Standard then, you can refer this AR#43989 , Since LVDS is not rail to rail voltage. If you satisfy the conditions mentioned in that you can interface with diffrent                               VCCO.

 

Hope you got the concept of interfacing, with different VCCO.

 

Regards,

Deepak D N

-----------------------------------------------------------------------------------------------------------

Please reply or give kudo or Accept As a Solution.

-----------------------------------------------------------------------------------------------------------

Regards,
Deepak D N
---------------------------------------------------------------------------
Please Kudo and Accept as a Solution, If it helps.
---------------------------------------------------------------------------

View solution in original post

Visitor
Visitor
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Registered: ‎11-10-2018
 
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