cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
632 Views
Registered: ‎07-04-2019

State machine failure

I'm having some trouble on understanding why my FSM is not making the necessary transitions. Quartus diagram does not show every arrow, basically. 

Hope you can help me.

 

0 Kudos
Reply
3 Replies
595 Views
Registered: ‎06-21-2017

Since you are having Quartus issues, I can't give detailed answers, but I have a couple points.  You should be writing one process state machines.  The case statement and output assignements should be in the registered process.  This helps to avoid latches and makes it a lot easier to get your process sensitivity list correct.  Have you simulated?  Provided your sensitivity list is correct, simulation can help to debug problems. 

Why are you asking questions about Quartus on a Xilinx board? 

 

Observer
Observer
569 Views
Registered: ‎07-05-2019

How are you checking if it is starting or no. Are you simulating on tool or checking it on hardware?

0 Kudos
Reply
Voyager
Voyager
541 Views
Registered: ‎08-16-2018

@henrique_martins 

If you are using Intel FPGAs, you should ask for help in Intel forums. For example, we cannot help with your image, it's another environment.

How do you know it fails? What is it that fails? Could you share a testbench and its result?

 

0 Kudos
Reply