07-04-2019 08:33 PM
07-05-2019 07:09 AM
Since you are having Quartus issues, I can't give detailed answers, but I have a couple points. You should be writing one process state machines. The case statement and output assignements should be in the registered process. This helps to avoid latches and makes it a lot easier to get your process sensitivity list correct. Have you simulated? Provided your sensitivity list is correct, simulation can help to debug problems.
Why are you asking questions about Quartus on a Xilinx board?
07-08-2019 06:17 AM - edited 07-08-2019 06:20 AM
If you are using Intel FPGAs, you should ask for help in Intel forums. For example, we cannot help with your image, it's another environment.
How do you know it fails? What is it that fails? Could you share a testbench and its result?