06-12-2019 12:03 AM
Hi,
I have a Zynq device which manages the configuration of a Spartan 7 FPGA through the Slave Serial Interface. The CCLK_0 and DIN pins of the FPGA are connected to the sclk and MOSI pins of the SPI1 bus, directly managed by the PS of the Zynq.
At the beginning I had some issues, which, after several tests, led me to the conclusion that the CCLK_0 pin of the Spartan7 has an internal weak pull-up (of about 15kohm). Indeed, if I disable the SPI controller of the Zynq device, I see the clock line go high, and it goes down again as soon as I enable the controller. I performed the very same test without connecting the clock line to the CCLK_0 pin and this time the voltage level is always zero, so the problem is not related to the Zynq PS, but to the Spartan 7. I think that when the SPI controller is disabled, the Zynq leaves those pins 3-stated and when it is enabled it directly drives them. Anyway, the problem is not with the Zynq, since the behaviour is different with or without the Spartan 7 connected.
By connecting a pull-down resistor in parallel, I managed to configure the FPGA and I realized that the pull-up resistance should be in the order of 15 kohm. I read UG 470 (https://www.xilinx.com/support/documentation/user_guides/ug470_7Series_Config.pdf) and in the Overview section I found:
Even if the Spartan 7 is in Slave configuration mode (M[2:0] = '111' SlaveSerial) and CCLK_0 should be an input, I think this pin has an internal weak pull-up (about 15 kohm). This could explain all the thing that I saw.
Can anyone tell me if this is true?
06-16-2019 11:18 PM
I repeated the test, which confirms the things I already saw: the CCLK_0 pin has a pull-up resistor, no matter if it is an input or an output.
06-16-2019 11:18 PM
I repeated the test, which confirms the things I already saw: the CCLK_0 pin has a pull-up resistor, no matter if it is an input or an output.