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joancab
Advisor
Advisor
388 Views
Registered: ‎05-11-2015

Synthesis and simulation

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I run synthesis and after that, post-synthesis simulation.

Now I changed something. Re-synthesize. Now: I don't open the synthesized design and relaunch the post-synthesis simulation.

I have the suspicion it is using the old synthesis. If I open the Synthesis tab in Flow Navigator it asks me to reload the new synthesized project.

joancab_0-1613062794092.png

 

So, is the correct flow: Synthesis - open synthesized project - relaunch simulation?

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kdeshwal
Xilinx Employee
Xilinx Employee
286 Views
Registered: ‎11-12-2019

@joancab ,

Yes you have to reload it to observe the latest effects.
Reload option would only comes if you change anything , let's say editing rtl or constraint file, after the synthesis has already been completed successfully.

 

Thanks,
Kuldeep

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6 Replies
346 Views
Registered: ‎01-22-2015

@joancab 

Even with plain "Behavioral Simulation", sometimes the changes I make in the HDL do not appear in subsequent simulation.  The following flow keeps simulation working "as expected" for me.

  1. Close the current simulation
  2. Make changes in the HDL and save the source file containing the HDL
  3. Reset the simulation (right-click on SIMULATION to get Reset window)
    reset_simulation.jpg

  4. Relaunch the simulation (which should automatically relaunch synthesis, if needed)
    run_simulation.jpg


TIP: resetting simulation, as shown above, should be done before archiving your Vivado project - since it deletes files (sometimes large) that need not be included in the archive.

Cheers,
Mark

kdeshwal
Xilinx Employee
Xilinx Employee
316 Views
Registered: ‎11-12-2019

Hi @joancab ,

To run the post-synthesis simulation, just verify that the synthesis runs successfully and then the Run Simulation → Post-Synthesis Timing Simulation option becomes available.

After synthesis, the general logic design has been synthesized into device-specific primitives. Performing a post-synthesis functional simulation ensures that any synthesis optimizations have not affected the functionality of the design. After you select a post-synthesis functional simulation, the functional netlist is generated, and the UNISIM libraries are used for simulation.

For detailed information, refer UG900.

Thanks,
Kuldeep

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joancab
Advisor
Advisor
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Registered: ‎05-11-2015

@kdeshwal I do that, but my question is if I have to reload the synthesized design before running post-synth sim. From my recent experience it looks like I need to.

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joancab
Advisor
Advisor
289 Views
Registered: ‎05-11-2015

markg@prosensing.com Yes, I also observed some funny things with behavioural. Nothing wrong with resetting everything, except for the little time each of these potentially unnecessary operations take, that at the end of the day make a significant amount for a full sim day as it was yesterday.

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kdeshwal
Xilinx Employee
Xilinx Employee
287 Views
Registered: ‎11-12-2019

@joancab ,

Yes you have to reload it to observe the latest effects.
Reload option would only comes if you change anything , let's say editing rtl or constraint file, after the synthesis has already been completed successfully.

 

Thanks,
Kuldeep

-------------------------------------------------------------------------------------------------------------
Please give Kudo and Accept as a Solution if solution provided seems helpful.
Have a look at our Versal Design Process Hub, Versal Blogs and the Versal Forum Useful Resources
-------------------------------------------------------------------------------------------------------------

View solution in original post

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joancab
Advisor
Advisor
257 Views
Registered: ‎05-11-2015

It's just a bit weird why one has to take an additional action (reload the new synthesized project) which is a potential source of errors. I cannot see the point in Vivado keeping an old synthesis.

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